A low-cost (with bare chips), high cooling ability and very low pressure drop 3D IC integration system-in-package (SiP) is designed and described. This system consists of a silicon interposer with through-silicon vias (TSV) and embedded fluidic microchannels, which carries all the Moore’s law chips and optical devices on its top and bottom surfaces. TSVs in the Moore’s law chips are optional but should be avoided. This novel structural design offers potential solutions for high-power, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost 3D IC SiP applications.

This content is only available via PDF.
You do not currently have access to this content.