Experimental and Simulation Study of the Effect of Power Package Configuration on its Thermal Performance

R_thJA (Junction-to-Ambient Thermal Resistance) for power device packages was measured and modeled in order to correlate the results from our experiments and simulations. The packages studied, including TO (Transistor Outline), DFN (Dual Flat Non-Leaded), SOP (Small Outline Package) and DPAK with sizes from 3×3mm to 15×10mm, were tested under natural convection environment. An important observation from our testing is the significant influence of the external wires connecting the test coupon to the power supply on the thermal resistance value derived from the test data. The increase in the R_thJA based on the test is more than 50% for TO packages and 19% for smaller packages once the external wires changed from gauge 18 to 30. A simple yet effective simulation approach was then introduced to predict R_thJA incorporating the critical influence from the external wire size variation. With the validated finite element model, the effects of package factors such as package outline, die size, die attach, encapsulation and interconnection on the thermal resistances of the power semiconductor packages were studied by simulation to provide further insights and guides for new package developments.