In this work, guided by electromagnetics-based first principles, we develop a circuit simulator that allows for the simulation of a circuit including both nonlinear devices and the linear network in linear complexity. Moreover, it permits an almost embarrassingly parallel implementation on a many-core computing platform, and hence achieving linear speedup. The proposed circuit simulator rigorously captures the coupling between nonlinear circuits and the linear network. In addition, it bypasses the step of extraction, producing an RLC (resistor-inductor-capacitor) representation of the linear network without any numerical computation. Application to die-package co-simulation as well as simulation of very large-scale on-chip circuits involving over 800,000 CMOS transistors and interconnects having hundreds of millions of unknowns has demonstrated the superior performance of the proposed first-principle-guided circuit simulator.
- Electronic and Photonic Packaging Division
A First-Principle Guided Circuit Simulator of Linear Complexity and its Linear Speedup for Die-Package Co-Design
He, Q, Chen, D, & Jiao, D. "A First-Principle Guided Circuit Simulator of Linear Complexity and its Linear Speedup for Die-Package Co-Design." Proceedings of the ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems. ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1. Portland, Oregon, USA. July 6–8, 2011. pp. 647-652. ASME. https://doi.org/10.1115/IPACK2011-52276
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