Modeling Fracture in Dielectric Stacks due to Chip-Package Interaction: Impact of Dielectric Material Selection

The trend towards decreasing dielectric constant of Interlayer Dielectric (ILD) materials has required significant trade-off between electrical performance and mechanical integrity of the die stack. Fracture caused by thermal stresses due to large coefficient of thermal expansion (CTE) mismatch between these materials arising during fabrication or testing are often the main driving force for failure. In this paper, we use CAD-inspired hierarchical field compositions [1] to carry out Isogeometric (meshfree) fracture simulations. We model cracks as arbitrary curves/surfaces and the crack propagation criterion is based on the evolving energy release rate (ERR) of the system. We simulate the solder reflow process to assess the impact of chip-package interaction on the reliability of ILD stacks. We use multi-level modeling to extract displacement boundary conditions for the local model of the ILD stack. Eight layers of metallization are considered in the ILD stack. We study the relative risks of replacing stronger dielectric (SiO2) with weaker dielectrics (SiCOH, ULK) on the criticality of preexisting flaws in the structure. Further, we study the impact of varying interfacial toughness values on the crack growth patterns in ILD stacks. Crack patterns reflect the propensity towards predominantly bulk failure with increasing interfacial toughness.