CMOS VLSI technology has been facing various technical challenges as the feature sizes scale down. To overcome the challenges imposed by the shrink of the conventional on-chip interconnect system in IC chips, alternative interconnect technologies are being developed: one of them is three dimensional chips (3D ICs). Even though 3D IC technology is a promising solution for interconnect bottlenecks, thermal issues can be exacerbated. Thermal-aware design and optimization will be more critical in 3D IC technology than conventional planar IC technology, and hence accurate temperature profiles of each active layer will become very important. In 3D ICs, temperature profile of one layer depends not only on its own power dissipation but also on the heat transferred from other layers. Thus, thermal considerations for 3D ICs need to be done in a holistic manner even if each layer can be designed and fabricated individually. Conventional grid-based temperature computation methods are accurate but are computationally expensive, especially for 3D ICs. To increase computational efficiency, we developed a matrix convolution technique, called Power Blurring (PB) for 3D ICs. The temperature resulting from any arbitrary power dissipation in each layer of the 3D chip can be computed quickly. The PB method has been validated against commercial FEA software, ANSYS. Our method yields good results with maximum error less than 2% for various case studies and reduces the computation time by a factor of ∼ 60. The additional advantage is the possibility to evaluate different power dissipation profiles without the need to re-mesh the whole 3D chip structure.
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ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability
July 19–23, 2009
San Francisco, California, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
978-0-7918-4360-4
PROCEEDINGS PAPER
Fast Thermal Analysis of Vertically Integrated Circuits (3-D ICs) Using Power Blurring Method Available to Purchase
Je-Hyoung Park,
Je-Hyoung Park
University of California, Santa Cruz, Santa Cruz, CA
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Ali Shakouri,
Ali Shakouri
University of California, Santa Cruz, Santa Cruz, CA
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Sung-Mo Kang
Sung-Mo Kang
University of California, Merced, Merced, CA
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Je-Hyoung Park
University of California, Santa Cruz, Santa Cruz, CA
Ali Shakouri
University of California, Santa Cruz, Santa Cruz, CA
Sung-Mo Kang
University of California, Merced, Merced, CA
Paper No:
InterPACK2009-89072, pp. 701-707; 7 pages
Published Online:
December 24, 2010
Citation
Park, J, Shakouri, A, & Kang, S. "Fast Thermal Analysis of Vertically Integrated Circuits (3-D ICs) Using Power Blurring Method." Proceedings of the ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability. ASME 2009 InterPACK Conference, Volume 2. San Francisco, California, USA. July 19–23, 2009. pp. 701-707. ASME. https://doi.org/10.1115/InterPACK2009-89072
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