In this study, the thermal simulations of 3 dimensional IC packages base on 4-layer vertical stacked die (bare die on bare die) with TSV (through silicon vias) and micro-bumps structure are conducted. The thermal models by finite volume method are developed for different geometrical parameters (TSV, micro-bumps distribution arrangement and spacer thickness) and material property (thermal conductivity of spacer). The thermal performance and the heat transfer mechanism for the stacked die package are analyzed for optimizing the geometrical and material parameters. Not only the temperature distributions but also the junction temperature and thermal resistances in 4-layer stacked die package with different multi-die power configurations are shown and discussed.

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