3-dimensional integrated circuit (3D IC) is a promising technology in today’s IC packaging industry. Since the technology is in infancy stages, many aspects of this technology are still under heavy investigation. Reliability of through silicon via (TSV) interconnects and interlayer bonding between the silicon layers are issues that become more complicated in 3D ICs due to complexity of the architecture and miniaturized interconnects. Optimizing design of these devices is essential in order to avoid short fatigue life of interconnects. This manuscript addresses the impact of design parameters such as die thickness, TSV diameter, TSV pitch, underfill thickness and underfill properties on thermo-mechanical durability of Direct Chip Attach (DCA) solder joints and TSV interconnects used in a 3D IC packages. A design was proposed where DCA is used to connect 4 layers of ICs and TSVs are used to connect the active layer of the dies to the second silicon layer. Solder joints, as small as 50-micron diameter, were used to attach silicon layers. A numerical experiment is designed to vary design parameters at 3 levels using L9 ortagonal array. A 3-dimensional model of the package was built and model was solved under an accelerated temperature cycle loading. Solder is considered as visco-plastic material and copper interconnects are assumed to follow bilinear isotropic hardening behavior. Two continuum damage models, energy partitioning and Coffin-Manson models, were used to assess the number of cycles to failure for solder joints and TSV copper interconnects respectively. Minitab software was used to analyze the result of experiment. The most influential factors on durability of solder interconnect are found to be underfill properties and height. However, the most influential factor on TSV durability is found to be TSV diameter. A non-linear response was observed for TSV pitch and diameter indicating that the optimum level may be in the range selected.

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