In the past decade, compact components such as Chip Scale Packages and flip chips were the work horses of miniaturization. However, emerging applications are now demanding even higher packaging density. In order to fulfill this requirement, three dimensional packaging was evolved. Advantages of three dimensional packaging structure include minimal conductor length and eliminate speed limiting inter chip interconnects. In order to reduce signal delays and to increase heat dissipation, lot of solutions like through silicon vias, thermal vias, stacking were implemented. Stacked packages are finding applications ranging from high-end servers to mobility products. Most common applications of stacked packages include high performance memory, DRAM, logic-memory stack, system in a package etc. Stacked packages can be package-on-package or die stacked (with several dice inside the same casing) or both. The thermo-mechanical design of package on package is very complex and often requires elaborate models and analysis with considerable CPU time. In this paper we have considered a package with both die stacking and package on package. In the first part of this study we considered a variety of cases resembling the applications that stacked CSP can go into. In this study, we have considered various geometries to optimize the design mechanically in thermo-cycling loading. The optimization function for this study is to minimize the package height without compromising its reliability in terms of thermo-cycles. “Package on package” family of packages is expensive to operate and to fabricate hence a prior simulation of various geometry of interconnects is necessary to understand how the package is going to behave in terms of number of cycles. In this study we have considered different thicknesses of die, die attach, top substrate and bottom substrate to optimize solder joint fatigue life. In this study SAC405 is considered.

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