Through silicon via (TSV) is a technology which allows devices to be connected three-dimensionally. Three dimensional vertical integration using TSV Cu interconnect can greatly increase the packaging density and is one of the most advanced and promising technologies for future IC packaging. However, Cu filling of void free through silicon via with high aspect ratio (AR≥10) has been a challenge for a long time. In this paper, successful fabrication of void free TSV with very high aspect ratio was demonstrated via electroplating process. Proper equipment and processing conditions for electroplating are required. The same equipment and similar chemicals and process conditions could also be applied to fabricate high quality redistribution line technology (RDL).
Skip Nav Destination
ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability
July 19–23, 2009
San Francisco, California, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
978-0-7918-4359-8
PROCEEDINGS PAPER
Copper Plating Process for Through Silicon Via With High Aspect Ratio in Advanced Packaging
Yu Hung Huang,
Yu Hung Huang
National Cheng Kung University, Tainan City, Taiwan
Search for other works by this author on:
Huei-Huang Lee,
Huei-Huang Lee
National Cheng Kung University, Tainan City, Taiwan
Search for other works by this author on:
Sheng-Jye Hwang,
Sheng-Jye Hwang
National Cheng Kung University, Tainan City, Taiwan
Search for other works by this author on:
Durn-Yuan Huang
Durn-Yuan Huang
Chung Hwa University of Medical Technology, Tainan County, Taiwan
Search for other works by this author on:
Yu Hung Huang
National Cheng Kung University, Tainan City, Taiwan
Huei-Huang Lee
National Cheng Kung University, Tainan City, Taiwan
Sheng-Jye Hwang
National Cheng Kung University, Tainan City, Taiwan
Durn-Yuan Huang
Chung Hwa University of Medical Technology, Tainan County, Taiwan
Paper No:
InterPACK2009-89163, pp. 9-14; 6 pages
Published Online:
December 24, 2010
Citation
Huang, YH, Lee, H, Hwang, S, & Huang, D. "Copper Plating Process for Through Silicon Via With High Aspect Ratio in Advanced Packaging." Proceedings of the ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability. ASME 2009 InterPACK Conference, Volume 1. San Francisco, California, USA. July 19–23, 2009. pp. 9-14. ASME. https://doi.org/10.1115/InterPACK2009-89163
Download citation file:
8
Views
Related Proceedings Papers
Related Articles
Development of G-Helix Structure as Off-Chip Interconnect
J. Electron. Packag (June,2004)
Micro Solder Joint Reliability and Warpage Investigations of Extremely Thin Double-Layered Stacked-Chip Packaging
J. Electron. Packag (March,2022)
An Investigation of Pool Boiling Heat Transfer on Single Crystal Surfaces and a Dense Array of Cylindrical Cavities
J. Heat Transfer (December,2013)
Related Chapters
Plating on Titanium and Zirconium
Industrial Applications of Titanium and Zirconium: Third Conference
Minority Carrier Diffusion Length Degradation in Silicon: Who is the Culprit?
Recombination Lifetime Measurements in Silicon
Influence of Iron and Copper on Minority Carrier Recombination Lifetime in Silicon
Recombination Lifetime Measurements in Silicon