Thermo-Mechanical Analysis of a Laser Diode Chip in an Opto-Electronic Package

It is a well-known fact that the lasers have wide variety of applications in diverse fields from medicine to communications [1]. Laser packaging involves appropriate materials selection and design to ensure that the laser performance meets the required specifications. In this paper, we present a GaAs based laser diode package design. The package design enables the laser diode chip to withstand the thermo-mechanical strains that are induced during the package assembly process as well as during the operating conditions. Excessive stresses in the chips could causes cracks in the chip. Excessive strains could cause un-desired spectral characteristics in the emitted light [2]. Therefore, the objective is to design a package that is tested and characterized to avoid these failure modes. This study presents numerical and experimental investigation of thermo-mechanical strains induced due to coefficient of thermal expansion (CTE) mismatch between various package components during assembly process. Finite element (FE) analysis is used to predict the displacements, tensile strains and stresses in the chip at various assembly processes. Digital Image Correlation (DIC) technique was used to measure the strains in the laser diode. Earlier, other researchers have used photo-luminescence methods and spectroscopic methods etc to measure packaging induced strains in the laser package [3]–[9]. The authors are not aware of any prior work where the DIC technique is applied on a very small chip for strain measurements Good correlation in displacements and strains was obtained between the model and the measurements, increasing confidence in the model. In addition, experiments were conducted to estimate the fracture strength of the GaAs to predict the chip failure based on the maximum principal stress criterion. The FE model was later used to conduct parametric study to analyze the impact of other factors on the chip stress such as substrate thickness, voids, thermal gradients in the package, surface irregularities in the chip etc. Experiments and model indicated that the designed package was robust enough and does not cause any damage to the chip.