Both thermal and intrinsic stresses that occur during thin-film processing and assembly processes dominate the final residual stress in thin film electronic devices. Since the residual stress causes the shift of electronic functions of dielectric and semiconductor materials, these shifts sometimes degrade their performance and reliability. Therefore, it is very important to measure and control the residual stress in thin-film-applied products. In this study, the changes of the electronic performance of MOS transistors by mechanical stress were measured by applying a four-point bending method. The stress sensitivity of the transconductance of NMOS transistors increased from about 1%/100-MPa to about 15%/100-MPa by decreasing the gate length of the transistors from 400 nm to 150 nm. One of the estimated important factors which dominated this increase was attributed to the interference of stress concentration fields occurred at the edges of gate-electrodes. The change of the residual stress in a transistor structure caused by deposition of thin films was analyzed by applying a finite element method (FEM). The estimated change was validated by experiment using originally developed stress sensing chips. The estimated change of the stress due to deposition of gate electrode tungsten film was about 25MPa. The measured average stress was about 20MPa and it agreed well with the estimated value. In addition, the change of the residual stress caused by the interference of the stress concentration fields between two gate-electrodes was validated by applying this stress sensing chip. The measured change of the stress caused by making fine slits by focused ion beam was about 70MPa and it agreed well with the estimated value of about 60MPa. It was confirmed, therefore, that both the thin film process-induced stress and the assembly-induced stress change the final residual stress in a transistor structure and the change can be evaluated by our stress-sensing chip quantitatively.
- Electronic and Photonic Packaging Division
In-Line Evaluation Method of the Intrinsic Stress of Thin Films Used for Transistor Structures
Kishi, H, Sasaki, T, Ueta, N, Suzuki, K, & Miura, H. "In-Line Evaluation Method of the Intrinsic Stress of Thin Films Used for Transistor Structures." Proceedings of the ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability. ASME 2009 InterPACK Conference, Volume 1. San Francisco, California, USA. July 19–23, 2009. pp. 239-245. ASME. https://doi.org/10.1115/InterPACK2009-89145
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