As electronic product becomes smaller and lighter with an increasing number of function, the demand for high density and high integration becomes stronger. In other aspect, IT (information technology) products supported on broadband network communication technologies. It changes from the cable communication by the digital circuit to the wire less communication by analogue and mixed-signal technologies. We have researched requirements for the design of next generation system in packaging module from the several points of view which include line width, pad pitch, clock, frequency, interconnection delay and number of passive components. Based on this, we presented a new concept packaging module model. The new module, silicon through integration platform, has through interconnection via, fine wiring build up layers, and embedded passives. This paper reports the result, which focus on the various electrical characteristics of silicon through substrate, and electrical simulation design technology for system in package. We have tried very accurate impedance matching design using 2D electromagnetic simulation and TDR (Time Domain Refrectometry) measurement technology. To investigate high frequency characteristic of hi-speed transmission line and silicon through interconnection, we have tried 3D electromagnetic simulation and VNA (vector network analyser) measurement. Thus, we have obtained good performance of high frequency transmission line and optimal design rule for system in package.
- Heat Transfer Division and Electronic and Photonic Packaging Division
Electrical Simulation Design Technology of Silicon Through Substrate
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Takano, T, Yamaguchi, M, Nakayama, K, Maruyama, T, Chujyo, S, Kuramochi, S, & Fukuoka, Y. "Electrical Simulation Design Technology of Silicon Through Substrate." Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. Advances in Electronic Packaging, Parts A, B, and C. San Francisco, California, USA. July 17–22, 2005. pp. 999-1004. ASME. https://doi.org/10.1115/IPACK2005-73339
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