Placing active circuitry directly underneath the bond pads is an effective way to reduce the die size, and hence to achieve lower cost per chip. The main concern with such design is the possible mechanical damage to the underlying circuitry during the wire bonding process. For example, the initial bond force and subsequent ultrasonic vibration may cause cracks within the dielectric layer. The cracks can penetrate through the active circuitry underneath, resulting in electrical failures to the silicon device. At the present time, most studies found in the literature rely heavily on experimental characterization to study pad integrity. The characterization typically involves building test devices and conducting real-life bonding test. On the other hand, while there are few studies attempting to describe the stress-strain behavior of the process by numerical simulations, most are based on either over-simplified models or incomplete analysis. Furthermore, nearly all of these studies failed to provide any correlation with real test data, and hence the accuracy of the analysis becomes questionable. In this paper, we have developed a finite element based methodology to study the stress behavior of bond pad structures during thermo-sonic wire bonding. Unlike most previous studies, which used 2-D models and plane-strain assumption, the current model captures the 3-D structure of the bond pad and gold ball. The incremental principal stress at the dielectric layer was used as the stress criterion to correlate with dielectric cracking, which is the dominant failure mode during our bonding experiments. The dynamic friction coefficient at the gold-aluminum interface is found to be responsible to the change in magnitude and location of the peak stress. To validate the simulation results, two engineering test chips were built and bonded. The dielectric cracks were found to correlate well with the incremental principal stress. Furthermore, we have shown that the interfacial friction model was able to account for the difference in crack pattern. The FE model is expected to study the relative crack resistance for other bonding over active circuitry pad structures currently under consideration.

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