Warpage is an important issue for IC packages after molding. Due to laminated structure of IC packages, significant warpage occurs owing to differences in shrinkage among constituent materials. Thermal shrinkage is usually considered as the main cause for IC warpage. However, cure induced warpage is also important during the molding process. Analysis without considering cure induced shrinkage can not predict the amount of warpage well. In this paper, TSOP LOC54L package product, which is manufactured by ChipMos Corporation, is used as the simulation model. The P-V-T-C (Pressure, Volume, Temperature, and Conversion) relation and CTE (Coefficients of Thermal Expansion) of an encapsulation material are used to predict the amount of warpage and experimentally verifying the results in this study. By comparing the simulations with the experiments, the preliminary results of the study indicate this approach is capable of estimating warpage in IC packages without prohibitive computational effort.

This content is only available via PDF.
You do not currently have access to this content.