The junction-to-case thermal resistance or Theta_JC is one of the important metrics used to evaluate the performance and reliability of a particular electronic package. Currently, there is no established JEDEC standard for a Theta_JC test fixture. This paper presents the results of computational fluid dynamic (CFD) modeling studies carried out to propose a simple and robust Theta_JC fixture. The theoretical Theta_JC value for a particular package was first obtained assuming idealized conditions. The model was then modified to incorporate actual fixture conditions. The objective is to design a tester fixture that reduces the Theta_JC measurement error, i.e. ideal vs. fixture. The effect of various design parameters on the measured Theta_JC value was investigated. Sensitivity studies included cavity or insulation configuration, cold plate size, thermocouple probe orientation, thermal interface materials, and applied power. Modeling results showed that, regardless of the insulation design, there was considerable heat loss through the test board on which the package was mounted. This resulted in a lower Theta_JC value measured, with errors up to 30%. To reduce the heat loss and measurement error, a heater was mounted at the bottom of the board and maintained at a temperature within 1 to 2°C of the junction temperature. Using this simple approach, the measurement error was reduced to around 6%. From the results of the study, an optimized prototype fixture design is proposed.

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