This paper presents a simple yet novel analytical approach to model the heat conduction in a Printed Circuit Board (PCB) by taking advantage of the large thermal conductivity contrast between the copper and glass-epoxy layers. The model provides a compact expression for the effective thermal resistance of a PCB and captures an approximate 2-dimensional temperature distribution within the PCB copper layer using simple one-dimensional fin equations in successive copper-glass epoxy layers. The results for effective thermal resistance and temperature distributions in copper layers agree within ±10% of those predicted using finite element (FEM) simulations. The present approach can significantly improve the system level thermal modeling and design of single and multi-component PCBs.
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ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
July 17–22, 2005
San Francisco, California, USA
Conference Sponsors:
- Heat Transfer Division and Electronic and Photonic Packaging Division
ISBN:
0-7918-4200-2
PROCEEDINGS PAPER
A Novel Scheme in Thermal Modeling of Printed Circuit Boards
Wenjun Liu,
Wenjun Liu
Carnegie Mellon University, Pittsburgh, PA
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Min-Young Lee,
Min-Young Lee
Carnegie Mellon University, Pittsburgh, PA
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Mehdi Asheghi
Mehdi Asheghi
Carnegie Mellon University, Pittsburgh, PA
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Wenjun Liu
Carnegie Mellon University, Pittsburgh, PA
Min-Young Lee
Carnegie Mellon University, Pittsburgh, PA
Younes Shabany
Flextronics, San Jose, CA
Mehdi Asheghi
Carnegie Mellon University, Pittsburgh, PA
Paper No:
IPACK2005-73268, pp. 385-391; 7 pages
Published Online:
March 4, 2009
Citation
Liu, W, Lee, M, Shabany, Y, & Asheghi, M. "A Novel Scheme in Thermal Modeling of Printed Circuit Boards." Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. Advances in Electronic Packaging, Parts A, B, and C. San Francisco, California, USA. July 17–22, 2005. pp. 385-391. ASME. https://doi.org/10.1115/IPACK2005-73268
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