In this manuscript, the impact of scaling on self-heating of silicon-on-insulator (SOI) transistors is investigated. Effect of temperature dependent phonon-boundary scattering in silicon thin films, which results in reduction in thermal conduction in the channel region, is incorporated into a electro-thermal simulation tool. Results of DC electro-thermal simulations are used to study drain current degradation due to self-heating and to obtain the thermal resistance of SOI devices as a function of gate length and silicon layer thickness. The device thermal resistance is increased by nearly a factor of 3 due to the scaling of gate length from 180nm to 10nm. Self-heating in SOI devices with gate length of 10nm can be responsible for up to 30% reduction in the saturation current and neglecting phonon-boundary scattering in the channel region may underestimate the degradation of drain current due to self-heating by nearly a factor of two.
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ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
July 17–22, 2005
San Francisco, California, USA
Conference Sponsors:
- Heat Transfer Division and Electronic and Photonic Packaging Division
ISBN:
0-7918-4200-2
PROCEEDINGS PAPER
Impact of Thermal Sub-Continuum Effects on Electrical Performance of Silicon-on-Insulator Transistors Available to Purchase
Keivan Etessam-Yazdani,
Keivan Etessam-Yazdani
Carnegie Mellon University, Pittsburgh, PA
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Rozana Hussin,
Rozana Hussin
Carnegie Mellon University, Pittsburgh, PA
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Mehdi Asheghi
Mehdi Asheghi
Carnegie Mellon University, Pittsburgh, PA
Search for other works by this author on:
Keivan Etessam-Yazdani
Carnegie Mellon University, Pittsburgh, PA
Rozana Hussin
Carnegie Mellon University, Pittsburgh, PA
Mehdi Asheghi
Carnegie Mellon University, Pittsburgh, PA
Paper No:
IPACK2005-73182, pp. 2087-2095; 9 pages
Published Online:
March 4, 2009
Citation
Etessam-Yazdani, K, Hussin, R, & Asheghi, M. "Impact of Thermal Sub-Continuum Effects on Electrical Performance of Silicon-on-Insulator Transistors." Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. Advances in Electronic Packaging, Parts A, B, and C. San Francisco, California, USA. July 17–22, 2005. pp. 2087-2095. ASME. https://doi.org/10.1115/IPACK2005-73182
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