Wafer level packaging has emerged as one of the promising solutions for hermetic packaging of MEMS devices. Detection of the level of hermeticity of the package is essential for reliability and design assessment of the devices. Traditionally, hermeticity has been tested using Helium based fine leak testing. However, there are limitations when this technique is used for the hermeticity detection of small volumes (< 10−3 cc) that are typical in wafer level packages. This paper reviews the helium fine leak test, its limitations and the influence of the different test parameters on leakage rate measurement are analyzed for wafer level packages with small cavity volumes. The results indicate a need for development of a new hermeticity measurement technique to achieve the measurement sensitivity required for wafer level packages.
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ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
July 17–22, 2005
San Francisco, California, USA
Conference Sponsors:
- Heat Transfer Division and Electronic and Photonic Packaging Division
ISBN:
0-7918-4200-2
PROCEEDINGS PAPER
On Hermeticity Detection of Wafer Level Packages for MEMS Devices
A. Goswami,
A. Goswami
University of Maryland, College Park, MD
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A. Chien
A. Chien
Agilent Technologies, Inc., San Jose, CA
Search for other works by this author on:
A. Goswami
University of Maryland, College Park, MD
B. Han
University of Maryland, College Park, MD
C. Wade
Agilent Technologies, Inc., San Jose, CA
A. Chien
Agilent Technologies, Inc., San Jose, CA
Paper No:
IPACK2005-73485, pp. 2067-2071; 5 pages
Published Online:
March 4, 2009
Citation
Goswami, A, Han, B, Wade, C, & Chien, A. "On Hermeticity Detection of Wafer Level Packages for MEMS Devices." Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. Advances in Electronic Packaging, Parts A, B, and C. San Francisco, California, USA. July 17–22, 2005. pp. 2067-2071. ASME. https://doi.org/10.1115/IPACK2005-73485
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