A variety of fabrication techniques have been used to make microfluidic microsystems: bulk etching in silicon and glass, plastic molding and machining, and PDMS (silicone) casting. Surprisingly the most widely used method of integrated circuit (IC) fabrication (surface micromachining — SMM) has not been extensively utilized in microfluidics despite its wide use in MEMS. There are economic reasons that SMM is not often used in microfluidics; high infrastructure and start-up costs and relatively long fabrication times: and there are technical reasons; packaging difficulties, dominance of surface forces, and fluid volume scaling issues. However, there are also important technical and economic advantages for SMM microfluidics relating to large-scale batch, no-assembly fabrication, and intimate integration of mechanical, electrical, microfluidic, and nano-scale sub-systems on one chip. In our work at Sandia National Laboratories MDL (Microelectronics Development Lab) we have built on the existing MEMS SMM infrastructure to produce a variety of microfluidic microsystems. These example microsystems illustrate the challenges and opportunities associated with SMM microfluidics. In this paper we briefly discuss two SMM microfluidic microsystems (made in the SUMMiT™ and SwIFT™ processes — www.mdl.sandia.gov/micromachine) in terms of technical challenges and unique SMM microfluidics opportunities. The two example microsystems are a DEP (dielectrophoretic) trap, and a drop ejector patterning system.
- Heat Transfer Division and Electronic and Photonic Packaging Division
Surface Micromachined Microfluidics: Example Microsystems, Challenges and Opportunities
- Views Icon Views
- Share Icon Share
- Search Site
Galambos, P, & James, C. "Surface Micromachined Microfluidics: Example Microsystems, Challenges and Opportunities." Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. Advances in Electronic Packaging, Parts A, B, and C. San Francisco, California, USA. July 17–22, 2005. pp. 2023-2032. ASME. https://doi.org/10.1115/IPACK2005-73491
Download citation file: