The recent trend in microprocessor architecture has been to increase the number of transistors (higher power), shrink processor size (smaller die), and increase clock speeds (higher frequency) in order to meet the market demand for high performance microprocessors. These have resulted in the escalation of power dissipation as well as the heat flux at the silicon die level. The Intel packaging technology development group has been challenged to develop packaging solutions that not only meet the package thermal targets but also the reliability requirements. As a result, an integrated heat spreading (IHS) package was developed, comprising a Cu based heat spreader and a first level thermal interface material (TIM) between the die and the heat spreader. Due to CTE mismatches between its different elements, the IHS package is subjected to high level of thermo-mechanical stresses which lead to severe failures post reliability testing. A significant amount of theoretical understanding of thermal resistance has been developed and applied to the development of TIM formulations, and it was found that the thermo-mechanical properties of the TIM material need to be optimized to mitigate the package reliability stresses. Several material and process solutions have been investigated using fundamental approaches, and, as a result of these efforts, low stress silicone gel TIM’s were developed. This paper provides an overview of the silicone gel TIM technologies investigated at Intel, and the key learnings from the fundamental material and package integration studies.

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