The bandwidth provided by optical interconnects makes them an attractive solution for chip-to-package and chip-to-chip communications. In such systems, chips will have optical I/O interconnects fabricated alongside their conventional electrical counterparts. Virtually no work has been previously reported relating to the testing of such chips at the wafer-level. The requirements for probe hardware needed to achieve this are identified, and probe module configurations based on these requirements are presented. A high-density micro-opto-electro-mechanical-systems (MOEMS)-based probe substrate prototype for interfacing with chips having electrical and optical polymer pillar-based I/Os has been designed, and built using microfabrication techniques. Successful probing of an array of polymer pillar-based optical I/Os is reported.
Skip Nav Destination
ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
July 17–22, 2005
San Francisco, California, USA
Conference Sponsors:
- Heat Transfer Division and Electronic and Photonic Packaging Division
ISBN:
0-7918-4200-2
PROCEEDINGS PAPER
Probe Module for Wafer-Level Testing of Gigascale Chips With Electrical and Optical I/O Interconnects
Hiren Thacker,
Hiren Thacker
Georgia Institute of Technology, Atlanta, GA
Search for other works by this author on:
Oluwafemi Ogunsola,
Oluwafemi Ogunsola
Georgia Institute of Technology, Atlanta, GA
Search for other works by this author on:
Muhannad Bakir,
Muhannad Bakir
Georgia Institute of Technology, Atlanta, GA
Search for other works by this author on:
James Meindl
James Meindl
Georgia Institute of Technology, Atlanta, GA
Search for other works by this author on:
Hiren Thacker
Georgia Institute of Technology, Atlanta, GA
Oluwafemi Ogunsola
Georgia Institute of Technology, Atlanta, GA
Muhannad Bakir
Georgia Institute of Technology, Atlanta, GA
James Meindl
Georgia Institute of Technology, Atlanta, GA
Paper No:
IPACK2005-73302, pp. 1593-1599; 7 pages
Published Online:
March 4, 2009
Citation
Thacker, H, Ogunsola, O, Bakir, M, & Meindl, J. "Probe Module for Wafer-Level Testing of Gigascale Chips With Electrical and Optical I/O Interconnects." Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. Advances in Electronic Packaging, Parts A, B, and C. San Francisco, California, USA. July 17–22, 2005. pp. 1593-1599. ASME. https://doi.org/10.1115/IPACK2005-73302
Download citation file:
8
Views
Related Proceedings Papers
Related Articles
Embedded Three-Dimensional Hybrid Integrated Circuit Integration System-in-Package With Through-Silicon Vias for Opto-Electronic Interconnects in Organic Substrates/Printed Circuit Boards
J. Electron. Packag (September,2011)
Device Process Integration: A New Device Fabrication Approach
J. Med. Devices (June,2010)
A Microfluidic Device to Establish Concentration Gradients Using Reagent Density Differences
J Biomech Eng (December,2010)
Related Chapters
An Adaptive Time-Division-Multiplexing Optical Networks-on-Chip
International Conference on Software Technology and Engineering (ICSTE 2012)
A Digital-to-Analog Converter for Extreme Environments
Intelligent Engineering Systems through Artificial Neural Networks, Volume 16
Engineering Design about Electro-Hydraulic Intelligent Control System of Multi Axle Vehicle Suspension
International Conference on Instrumentation, Measurement, Circuits and Systems (ICIMCS 2011)