In the near future, it is likely that the interconnection pitch of flip chips will fall below 100 microns. For a flip chip of 20mm × 20mm at this pitch, there will be 40,000 interconnections on the chip. Even after taking advantage of symmetry whereby only a one-eighth model need be analyzed, there will be 5,000 interconnections. If solder were used to form the interconnection, plasticity and creep effects would need to be taken into account. Despite the great advances in computer technology, the computer memory and computation time required for a full 3D finite element analysis (FEA) of such a fine-pitch IC package is prohibitive. This paper presents a slim sector model which could be used to overcome this problem. Essentially, a slim sector of the package adjacent to the diagonal is analyzed rather than a 1/8 model. The appropriate boundary condition to be applied to the slim sector model is a critical issue. With the large number of interconnections, it is reasonable to expect that the displacement of points close to the diagonal plane of the package will tend to be directed radially outwards from the neutral point at the centre of the package. The validity of this assumption was investigated by performing a full 3D FEA of the 1/8 model of two flip chip packages of dimensions 4mm square and 6mm square. A few slim sector models have been developed and their accuracy and computational efficiency studied. The fatigue life of the critical solder joint was determined by performing a temperature cycling simulation between −40C and 150C. The elastoplastic and creep properties of solder were taken into account. As the 1/8 model is the most accurate model, its results were taken as reference. It was found that the accuracy of the best slim sector model ranged between 12% and 27%. A comparison was also made between the slim sector model and the popular strip model. It was found that the slim sector model was much more accurate than the strip model which gives error of 61–248%.

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