In this paper, a state of the art TDR with a rise time of 9ps was employed in the characterization of multi-layer ball-grid array (BGA) or land-grid array (LGA) packages. The hardware used for 9ps rising time was the Picosecond Pulse Lab’s 4022 Source Enhancement Module that reduces a standard TDR rise time of 35–40ps to 9ps. The high-resolution TDR can clearly indicates a root cause of a multi-layer package signal integrity problem (impedance mismatching) in vertical transitions consisting of vias and planes which cannot be observed with a conventional TDR. In addition, due to its high-resolution, it was observed that the size of characteristic impedance testing transmission lines can be significantly scaled down. For example, a minimum length of 15–20 mm long transmission lines with a standard TDR can be reduced down to 3–4mm long for 9ps TDR. Using the TDR waveforms, reflection loss S11 (dB) was computed using direct convolution method and short-open-load (SOL) calibration method. The resulting (TDR generated) S11 agrees excellently with direct vector network analyzer (VNA) measurements up to 50 GHz which is the highest frequency available with Agilent 8364A.
- Heat Transfer Division and Electronic and Photonic Packaging Division
Realization of Ultra-Wideband, High-Resolution TDR for Chip-Carrier Packages
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Han, D, Xu, B, Choi, MJ, He, J, Gardiner, S, & Lee, C. "Realization of Ultra-Wideband, High-Resolution TDR for Chip-Carrier Packages." Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. Advances in Electronic Packaging, Parts A, B, and C. San Francisco, California, USA. July 17–22, 2005. pp. 1499-1503. ASME. https://doi.org/10.1115/IPACK2005-73291
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