Flip chip technology offers a number of advantages over conventional packaging techniques such as smaller size and efficient high-speed signal transmission. However, when assembled on organic substrates, the flip chip needs to be underfilled with a suitable adhesive to enhance the thermo-mechanical reliability of its solder bumps. When such flip chip assemblies are subjected to thermal excursions, the underfill material may delaminate resulting in premature solder bump fatigue failure. Available open literature has extensively focused on underfill delamination propagation due to monotonic loading conditions. However, the information on underfill fatigue delamination propagation is limited. This paper presents an experimental and modeling study on the underfill delamination under monotonic as well as fatigue loading conditions. In this work, the fracture toughness of the passivation-underfill interface has been characterized using the single leg bending test. In addition, a fatigue delamination propagation experiment has been done, and a Paris law type model for delamination propagation has been developed. In parallel, numerical models have been developed to determine the available energy release rate under monotonic loading conditions as well as the range of energy release rate range under thermal cycling conditions. The mode mixity calculations have been carried out using Crack Surface Displacement (CSD) method. Using the models and the experimental data, guidelines against the delamination of the underfill material are developed.
- Heat Transfer Division and Electronic and Photonic Packaging Division
A Fracture Mechanics Analysis of Underfill Delamination in Flip Chip Packages
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Mahalingam, S, Tonapi, S, & Sitaraman, SK. "A Fracture Mechanics Analysis of Underfill Delamination in Flip Chip Packages." Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. Advances in Electronic Packaging, Parts A, B, and C. San Francisco, California, USA. July 17–22, 2005. pp. 1341-1346. ASME. https://doi.org/10.1115/IPACK2005-73493
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