Experimental and Numerical Evaluation of Residual Stress in IC Chips

The high residual stress in an electronic package sometimes causes not only mechanical failure but also the instability of electronic functions. Therefore the residual stress in resin-molded electronic packages should be evaluated. In this paper, the residual stress in a resin-molded electronic package was evaluated by the combination of experimental method using a test chip including piezoresistive gauges and the finite element method (FEM). The linear thermal elastic analysis of the resin-molded electronic package was carried out using the three dimensional FEM model. Stress-free temperature for the analysis was experimentally determined using the piezoresistive test chip. It was demonstrated that the residual stress at room temperature obtained by the FEM analysis well corresponds with the stress measured using the test chip. It was found from the results that compressive residual stress of over 100MPa was distributed on the top surface of a semiconductor chip in a plastic package. This study presents a simple evaluation technology of the residual stress in resin-molded semiconductor chips using the combination of experimental and numerical methods.