The alarming growth of power increase has presented numerous packaging challenges for high performance processors. The average power consumed by a processor is the sum of dynamic and leakage power. The dynamic power is proportional to V^2, while the leakage current (therefore leakage power) is proportional to V^b where V is the voltage and b>1 for modern processes. This means lowering voltage reduces energy consumed per clock cycle but reduces the maximum frequency at which the processor can operate at. Since reducing voltage reduces power faster than it does frequency, integrating more cores into the processor would result in better performance/power efficiency but would generate more memory accesses, driving a need for larger cache and high speed signaling [1]. In addition, the design goal to create unified package pinout for both single core and multicore product flavors adds additional constraint to create a cost effective package solution for both market segments. This paper discusses the design strategy and performance of dual die package to optimize package performance for cost.
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ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference
July 17–22, 2005
San Francisco, California, USA
Conference Sponsors:
- Heat Transfer Division and Electronic and Photonic Packaging Division
ISBN:
0-7918-4200-2
PROCEEDINGS PAPER
Dual Die Package Design Strategy and Performance Available to Purchase
Mahadevan Suryakumar,
Mahadevan Suryakumar
Intel Corporation, Chandler, AZ
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Lu-Vong T. Phan,
Lu-Vong T. Phan
Intel Corporation, Chandler, AZ
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Wajahat Ahmed
Wajahat Ahmed
Intel Corporation, Chandler, AZ
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Mahadevan Suryakumar
Intel Corporation, Chandler, AZ
Lu-Vong T. Phan
Intel Corporation, Chandler, AZ
Mathew Ma
Intel Corporation, Chandler, AZ
Wajahat Ahmed
Intel Corporation, Chandler, AZ
Paper No:
IPACK2005-73391, pp. 1045-1051; 7 pages
Published Online:
March 4, 2009
Citation
Suryakumar, M, Phan, LT, Ma, M, & Ahmed, W. "Dual Die Package Design Strategy and Performance." Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. Advances in Electronic Packaging, Parts A, B, and C. San Francisco, California, USA. July 17–22, 2005. pp. 1045-1051. ASME. https://doi.org/10.1115/IPACK2005-73391
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