A solution space design methodology is presented for optimization of off-chip inductors. The analysis has been performed for an advanced wafer level redistribution manufacturing process. Electromagnetic simulations were performed to extract the characteristics of different inductor designs. It was observed that the design optimization should be tuned to the operating frequency.
- Electronic and Photonic Packaging Division
Design Optimization of Off-Chip Inductors
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Jin, L, Lu, ACW, Wai, LL, Fan, W, Tan, AC, & Chan, KC. "Design Optimization of Off-Chip Inductors." Proceedings of the ASME 2003 International Electronic Packaging Technical Conference and Exhibition. 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2. Maui, Hawaii, USA. July 6–11, 2003. pp. 735-739. ASME. https://doi.org/10.1115/IPACK2003-35223
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