Flip Chip Ball Grid Array (FCBGA) has been a common package technology to achieve higher Input/Output (IO) count. In moving toward higher IO count without increasing the package size, FCBGA package with tighter pitch is required. Unfortunately, ball pitch reduction from 1.27mm to 1mm in FCBGA packages is not a transparent change. Instead, it provides an inside into the thermo-mechanical performance of FCBGA solder joint. Previous study indicated the importance of the package solder resist opening-to-board pad size ratio (AR) as the dominant factor in improving the thermo-mechanical performance of the solder joint at one solder system. An optimum range of AR had been defined as failure free zone with respect to the temperature cycling stress from −40degC to 85degC. This paper is a continued study, which focused on identifying the optimum range of AR for failure free zone. Key factors under the study are package solder resist opening (SRO), die size, population pattern, type of board pad, type of package design and thermal solution. This paper consolidates the modeling and empirical data on the relationship. The results of the study has brought towards an identification of process window for 1mm pitch FCBGA package and led to package and board design rules in terms of targeted SRO & board pad size, type of pad design and a tightening of SRO & board pad size specification. Besides, the learning has led towards a new look into the BGA package certification in which SRO and board pad size are key factors in the design consideration.
Skip Nav Destination
ASME 2003 International Electronic Packaging Technical Conference and Exhibition
July 6–11, 2003
Maui, Hawaii, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
0-7918-3690-8
PROCEEDINGS PAPER
Effect of Package and Board Pad Size on Optimum Flip Chip Ball Grid Array (FCBGA) Package Thermo-Mechanical Performance
Chee Wai Wong,
Chee Wai Wong
Intel Products, Penang, Malaysia
Search for other works by this author on:
Cheng Siew Tay,
Cheng Siew Tay
Intel Products, Penang, Malaysia
Search for other works by this author on:
Shaw Fong Wong
Shaw Fong Wong
Intel Technology
Search for other works by this author on:
Chee Wai Wong
Intel Products, Penang, Malaysia
Cheng Siew Tay
Intel Products, Penang, Malaysia
Siew Sang Tan
Intel Technology
Vasu Vasudevan
Intel Corporation
Eng Huat Goh
Intel Technology
Shaw Fong Wong
Intel Technology
Paper No:
IPACK2003-35143, pp. 783-790; 8 pages
Published Online:
January 5, 2009
Citation
Wong, CW, Tay, CS, Tan, SS, Vasudevan, V, Goh, EH, & Wong, SF. "Effect of Package and Board Pad Size on Optimum Flip Chip Ball Grid Array (FCBGA) Package Thermo-Mechanical Performance." Proceedings of the ASME 2003 International Electronic Packaging Technical Conference and Exhibition. 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1. Maui, Hawaii, USA. July 6–11, 2003. pp. 783-790. ASME. https://doi.org/10.1115/IPACK2003-35143
Download citation file:
8
Views
Related Proceedings Papers
Related Articles
Reliability of Fine Pitch Sn–3.8Ag–0.7Cu Flip Chip Solder Joints With Different Connection Pads on PCB
J. Electron. Packag (March,2008)
Comparative Studies on Solder Joint Reliability of Plastic and Ceramic Ball Grid Array Packages of the Same Form Factor Under Power and Accelerated Thermal Cycling
J. Electron. Packag (December,2008)
Nonlinear Analysis of Full-Matrix and Perimeter Plastic Ball Grid Array Solder Joints
J. Electron. Packag (September,1997)
Related Chapters
Layer Arrangement Impact on the Electromechanical Performance of a Five-Layer Multifunctional Smart Sandwich Plate
Advanced Multifunctional Lightweight Aerostructures: Design, Development, and Implementation
Microstructure Evolution and Physics-Based Modeling
Ultrasonic Welding of Lithium-Ion Batteries
Prediction of Failures in Service by Photoelastic Methods
Advanced Testing Techniques