With the proliferation of flip chip packaging and multiple metal layer technology in advanced semiconductor integrated circuits (IC’s), traditional front-side probing and failure analysis tools are no longer viable. Full transistor level access from the substrate side (i.e., backside) of the chip is now required to fully realize such investigative work. Silicon is transmissive in the near-IR above its bandgap (≅ 1,000nm to 1,100nm). As a result, transistor level access can be achieved by optical means. To enable such optical access, it is necessary to first remove all heat dissipating devices such as finned heat sinks and integrated heat spreaders placed in contact with the silicon substrate. For most applications, the silicon is then mechanically thinned down to approximately 100μm, and a microscope objective is used to “probe” the chip optically for diagnostics and failure analysis. During such diagnostics and failure analysis, the device under test (DUT) is electrically exercised typically “at speed”, which translates into high power dissipation levels. A thermal management system that can be physically and optomechanically integrated with state-of-the-art diagnostics and failure analysis systems, and can dissipate significant power levels is required to maintain the DUT’s temperature equilibrium and avoid thermal runaway, that could irreversibly damage the DUT. One possible and efficient solution is provided by spraying a dielectric coolant directly onto the chip. In the present study, a test chip was used in conjunction with an exact model of a novel microscope objective that is in full contact with the device. The test chip was powered in increments from 0 to 82W/cm2, and the device level temperature was measured by several temperature sensors embedded in the chip. A spray head was designed to deliver conditioned coolant to the test chip’s surface, while simultaneously accommodating the obstruction of the microscope objective and allowing full optical access to the entire chip surface. Thermal performance results for the cooling system are provided for uniform heat flux levels of 30, 52, and 82W/cm2, with the optical probe located in the worst-case center of the test chip. For all heat fluxes studied, the maximum device level temperature did not exceed 60°C, the across-chip temperature differential was approximately 31°C, and surface temperature fluctuations were seen to have a standard deviation of less than ±1°C. The results are discussed in-depth, and are put in perspective of industry needs.
- Electronic and Photonic Packaging Division
Spray Cooling Thermal Management of a Semiconductor Chip Undergoing Probing, Diagnostics, and Failure Analysis
Ansari, S, Cader, T, Stoddard, N, Tolman, B, Frank, J, Cotton, D, Wong, T, & Pakdaman, N. "Spray Cooling Thermal Management of a Semiconductor Chip Undergoing Probing, Diagnostics, and Failure Analysis." Proceedings of the ASME 2003 International Electronic Packaging Technical Conference and Exhibition. 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1. Maui, Hawaii, USA. July 6–11, 2003. pp. 73-80. ASME. https://doi.org/10.1115/IPACK2003-35206
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