Optical interconnections at the chip level may provide solutions to the limitations of metal interconnect technology, which is not keeping pace with the progress of device integration density. In this paper we undertake a quantitative analysis of on-chip metal interconnect performance as CMOS device technology scales into the nanometer regime. The results of this analysis motivates the use of optical interconnects as a replacement for global wires on the chip. We propose a new architecture, in which a 3-D optoelectronic Application Specific Interconnection Fabric (ASIF) is coupled to a conventional Silicon integrated circuit to alleviate the performance-limiting aspects of long metal interconnects. The overall goal of the ASIF concept is to overcome the limitations of conventional metal interconnects in a manner that can be seamlessly integrated according to current VLSI design constraints and practices.

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