High-density, small spot size, and high power consumption have imposed both a technical and an economic challenge on optoelectronic (OE) packaging. Device non-uniformity and dynamic operating environments cause device performance variations, especially in applications where large OE arrays are employed. We describe our work to explore the opportunities in transceiver circuit design to relax optical alignment requirements, provide efficient thermal management, and allow dynamic variation within the optical system. Our approach focuses on a built-in power negotiation algorithm, which is developed to dynamically optimize the power consumption of optical links based on the bit error rate (BER) of each optical link. This algorithm can be executed as the system is powered up or during normal system operation if the link is idle or a change has been made. It converges to an optimal setting for each vertical cavity surface emitting lasers (VCSEL) that has the minimum power consumption for a given target BER. The intelligence of the dynamic power optimization provides the system with the capability of compensating for the potential variations in the system and therefore, relaxing the packaging requirements. We implement this algorithm in a 0.5μm CMOS silicon-on-insulator (SOI) chipset and develop parallel optical transceivers based on VCSELs and photodetectors to demonstrate the benefit of our approach. We build a field programmable gate arrays (FPGA) based test bed where both fiber optic and free-space optical interconnects are used for communications between two chips. Test results show that the algorithm is able to find the optimum power setting for all VCSELs despite varied light attenuation in optical path.
- Electronic and Photonic Packaging Division
Packaging Friendly Parallel Optical Transceivers
Wang, X, Kiamilev, F, Papen, G, Ekman, J, Gui, P, Haney, M, Deroba, J, McFadden, M, & Kuznia, C. "Packaging Friendly Parallel Optical Transceivers." Proceedings of the ASME 2003 International Electronic Packaging Technical Conference and Exhibition. 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1. Maui, Hawaii, USA. July 6–11, 2003. pp. 629-637. ASME. https://doi.org/10.1115/IPACK2003-35111
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