A technique is presented which allows a data center designer or operator to achieve any desired partitioning of available airflow among the floor tiles of a raised-floor data center without resorting to trial-and-error. The output from the analysis is a tile-by-tile prescription of flow resistance characteristics (e.g., damper settings), which accomplishes the desired partitioning. The technique is derived from an electrical-circuit analogy of the airflow in the data. Each circuit branch represents one path that air may follow from the CRAC unit supply, through a particular floor tile, and ultimately back to the CRAC return. Any desired flow partitioning through tiles can be achieved by proper adjustment of tile resistances in each circuit; however, by itself, the flow network has too many unknowns to be solvable. A CFD simulation of the entire data center, in which the desired flow partitioning is specified, provides the pressure distribution above (in the room) and below (in the plenum) the floor tiles. The method is illustrated in step-by-step fashion with a simple example case.
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ASME 2003 International Electronic Packaging Technical Conference and Exhibition
July 6–11, 2003
Maui, Hawaii, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
0-7918-3690-8
PROCEEDINGS PAPER
A Hybrid Flow Network-CFD Method for Achieving Any Desired Flow Partitioning Through Floor Tiles of a Raised-Floor Data Center
James W. VanGilder,
James W. VanGilder
Flomerics, Inc., Southborough, MA
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Ted Lee
Ted Lee
Flomerics, Inc., Santa Clara, CA
Search for other works by this author on:
James W. VanGilder
Flomerics, Inc., Southborough, MA
Ted Lee
Flomerics, Inc., Santa Clara, CA
Paper No:
IPACK2003-35171, pp. 377-382; 6 pages
Published Online:
January 5, 2009
Citation
VanGilder, JW, & Lee, T. "A Hybrid Flow Network-CFD Method for Achieving Any Desired Flow Partitioning Through Floor Tiles of a Raised-Floor Data Center." Proceedings of the ASME 2003 International Electronic Packaging Technical Conference and Exhibition. 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1. Maui, Hawaii, USA. July 6–11, 2003. pp. 377-382. ASME. https://doi.org/10.1115/IPACK2003-35171
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