This paper investigates thermo-mechanical deformation and stresses of a flip-chip package (FCBGA) with and without underfill materials. Chip carrier is a 2-2-2 build-up substrate with 40 × 40 mm2 dimension; while bump material employs Sn/37Pb eutectic solder. Temperature-dependent warpage (out-of-plane displacement) of a FCBGA is characterized via shadow moire´ technique. Results of warpage measurement reveal that packages do not follow the same path during thermal loading/unloading cycle (20-220-20 °C) for both FCBGA with and without underfills. This implies that both solder and underfill exhibit inelastic material response. Therefore, it is a necessity to consider nonlinear constitutive response of packaging materials when designing flip-chip packages. It is observed that FCBGA with underfill exhibit more warpage than packages without underfill due to higher CTE mismatch between underfills and silicon dies. Aspect of package geometry such as die-to-substrate thickness ratio is found to play important role in reducing package stresses. Especially, thinner die provides more direct impact to die stresses reduction than thinner substrate does.

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