Development of higher performance silicon products often leads to more stringent demands on power delivery. Higher current sustainability is often a key parameter in successful power delivery design. One potential bottleneck in the delivery of power to the component is the printed circuit board (PCB) to component interface. However in many designs, the same interconnect structure is used for both the power and signal connection even though the requirements for power and signaling can be different. For example in current art, a substantially similar solder ball and pad design is used for both power and signal connections. This results in interconnects that may not be optimized for high current power delivery, and in turn lead to unnecessarily high power loss at the interconnect. Under this design archetype, higher current generally requires more power/ground solder balls and thus larger packages. In addition, these power connections compete with much-needed IO connections on the component. This paper discusses methods for separating and optimizing the power and signal interconnect structures. Example proof-of-concept instances are given using different component/board layout patterns and surface mount technology (SMT) structures. For example, one of these instances involves increasing BGA solder density to the point where solder may gang together during board assembly reflow (a design called ganged solder). Another example involves varying the board pad and via layout pattern and depth to accompany optimized high current socket contacts. The data indicates that employing such separation and optimization techniques can lead to a substantial drop in board and interconnect resistance. In each case, voltage gradient, temperature and resistance data is collected, and relative performance trends are discussed.

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