High density and integrated packaging of electronic device requires fine pitch. This packaging causes reliability problem in electronic device. One of them, warpage of the package occurred at chip assembly process may affect reliability. Therefore, if the simulation at the time of a chip assembly process is possible, it will be able to evaluate warpage in advance. It is very effective for development of a new product. Then, in this paper, the build-up package is regarded as a single material and the simulation technique of accuracy warpage at the time of chip assembly is reported. Next it is investigated the simulation technique for package warpage at the chip assembly process. Finnaly, it analyzed about the properties which affect warpage.
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ASME 2003 International Electronic Packaging Technical Conference and Exhibition
July 6–11, 2003
Maui, Hawaii, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
0-7918-3690-8
PROCEEDINGS PAPER
Influence of the Property of the Build-Up Package on Warpage at Flip Chip Assembly Process
Yukihiko Toyoda,
Yukihiko Toyoda
Ibiden Company, Ltd., Gifu, Japan
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Yoichiro Kawamura,
Yoichiro Kawamura
Ibiden Company, Ltd., Gifu, Japan
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Hiroyoshi Hiei,
Hiroyoshi Hiei
Ibiden Company, Ltd., Gifu, Japan
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Qiang Yu,
Qiang Yu
Yokohama National University, Yokohama, Japan
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Tadahiro Shibutani,
Tadahiro Shibutani
Yokohama National University, Yokohama, Japan
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Doseop Kim,
Doseop Kim
Yokohama National University, Yokohama, Japan
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Haeki Nam
Haeki Nam
Yokohama National University, Yokohama, Japan
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Yukihiko Toyoda
Ibiden Company, Ltd., Gifu, Japan
Yoichiro Kawamura
Ibiden Company, Ltd., Gifu, Japan
Hiroyoshi Hiei
Ibiden Company, Ltd., Gifu, Japan
Qiang Yu
Yokohama National University, Yokohama, Japan
Tadahiro Shibutani
Yokohama National University, Yokohama, Japan
Doseop Kim
Yokohama National University, Yokohama, Japan
Haeki Nam
Yokohama National University, Yokohama, Japan
Paper No:
IPACK2003-35262, pp. 197-201; 5 pages
Published Online:
January 5, 2009
Citation
Toyoda, Y, Kawamura, Y, Hiei, H, Yu, Q, Shibutani, T, Kim, D, & Nam, H. "Influence of the Property of the Build-Up Package on Warpage at Flip Chip Assembly Process." Proceedings of the ASME 2003 International Electronic Packaging Technical Conference and Exhibition. 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1. Maui, Hawaii, USA. July 6–11, 2003. pp. 197-201. ASME. https://doi.org/10.1115/IPACK2003-35262
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