The purpose of this research was to produce semiconductor Rutile TiO 2 films using a new deposition method on F-doped SnO 2 (FTO) glasses i.e. nanofluid boiling method, using TiO 2 nanoparticles. A low-temperature synthesis without using conventional hydrothermal methods was established to obtain the Rutile TiO 2 nanoparticles with different size and shape under different temperatures. The crystalline TiO 2 was separated from the reaction liquid by centrifugation and dried under ambient condition. The current boiling deposition of the TiO 2 nanofluid was found to form porous semiconductor TiO 2 nanoparticle films without cracks in the deposited TiO 2 film. The obtained TiO 2 films will be utilized as TiO 2 photoanodes in dye-sensitized solar cells.

Silicon carbide (SiC) is a useful semiconductor material due to its high thermal conductivity (λ), low reactivity, and high strength. These properties also make it an ideal nuclear fuel cladding material. Because heat transfer in SiC is dominated by phonons, there is value in understanding how different phonon branches contribute to λ. To accomplish this, it is useful to run simulations which employ fewer phonon branches than normally exist. In materials where phonons dominate heat transport, such as SiC, the Monte Carlo method as applied to phonon transport is suitable for estimating λ. This work uses the Monte Carlo method to estimate λ of 3C-SiC using four phonon branches, namely, transverse acoustic (TA), longitudinal acoustic (LA), transverse optical (TO), and longitudinal optical (LO). By adding branches into the simulation and measuring λ, the individual contributions to λ from each branch can be determined.

Power semiconductor devices such as MOSFET/IGBT and PiN diodes are widely used as basic components for supporting infrastructure in the field of electronics, including in power conversion, industrial equipment, railways, and automobiles. Recently, increasing attention has been paid to silicon carbide (SiC) as a wide-band-gap semiconductor suitable for use in power devices with low loss and high breakdown voltage. However, basic knowledge of the material properties and reliability of SiC devices, and particularly the influence of mechanical stress on device characteristics, is still incomplete. In this paper, we evaluated the effect of mechanical stress on the electrical characteristics of SiC devices. In order to investigate the effect of stress on the SiC device characteristic, we propose a simple evaluation method using four-point bending, which is a classical method capable of applying uniaxial stress to a device. With this method, we evaluated the stress in a SiC device using residual stress measurement by Raman spectroscopy and stress simulation based on the finite element method. Our proposed experimental method is as follows. First, the SiC device was bonded with AuGe solder to a metal plate [phosphor bronze; Young’s modulus: 105 GPa; Poisson’s ratio: 0.33; dimensions: 100 mm (W) × 12 mm (L) × 2 mm (T)], and aluminum wire (wire radius: 200 μm) was also bonded to the device. Second, the prepared device was placed on the specially designed four-point bending apparatus for mechanical stress experiments. Finally, the sample was bent in compression or tension in the in-plane direction by the four-point system. The SiC device was subjected to compression or tensile stress via the metal plate. The electrical characteristics of the SiC-MOSFET were measured with a curve tracer in our proposed system. I d − V ds characteristics changed linearly as stress was applied to the device. As a result, the on-resistance was increased by 7.6% by applying a tensile stress of 300 MPa and was decreased by 1.0% by applying a compressive stress of 100 MPa at room temperature, respectively. A power device circuit with multiple chips was also simulated by SPICE based on the experimental results to confirm the effects of stress on SiC devices in a power module. Simulated MOSFET model contains stress factors obtained from experimental results. The circuit was simulated by electro-thermal coupled analysis using a one-dimensional model of the electric circuit and thermal circuit constructed in SPICE. The results show that the proposed method is powerful simulation method for power device design.

Stretchable electronics have been a subject of increased research over the past decade [1–3]. Although stretchable electronic devices are a relatively new area for the semiconductor/electronics industries, recent market research indicates the market could be worth more than 900 million dollars by 2023 [4]. At CES (Consumer Electronics Show) in January 2016, two commercial patches were announced which attach to the skin to measure information about the user’s vitals and environmental conditions [5]. One of these measures the sun exposure of the user with a UV sensitive dye — which can communicate with the user’s cell phone to track the user’s sun exposure. Another device is a re-usable flexible patch which measures cardiac activity, muscle activity, galvanic skin response, and user’s motion. These are just two examples of the many devices that will be developed in the coming years for consumer and medical use. This paper investigates mechanical testing methods designed to test the stretching capabilities of potential products across the electronics industry to help quantify and understand the mechanical integrity, response, and the reliability of these devices. Typically, the devices consist of stiff modules connected by stretchable traces [6]. They require electrical and mechanical connectivity between the modules to function. In some cases, these devices will be subject to bi-axial and/or cyclic mechanical strain, especially for wearable applications. The ability to replicate these mechanical strains and understand their effect on the function of the devices is critical to meet performance, process and reliability requirements. There has been a test method proposed recently for harsh / high-rate testing (shock) of stretchable electronics [7]. The focus of the approach presented in the paper aims to simulate expected user conditions in the consumer and medical fields, whereas earlier research was focused on shock testing. In this paper, methods for simulating bi-axial and out-of-plane strains similar to what may occur in a wearable device on the human body are proposed. Electrical and / or optical monitoring (among other methods) can be used to determine cycles to failure depending on expected failure modes. Failure modes can include trace damage in stretchable regions, trace damage in functional component regions, or bulk stretchable material damage, among others. Three different methods of applying mechanical strain are described, including a stretchable air bladder method, membrane test method, and lateral expansion method. This work will describe a prototype of the air bladder method with initial results of the testing for example devices. The system utilizes an expandable bladder to roughly simulate the expansion of muscles in the human body. Besides strain and # of cycles, other variables such as humidity, temperature, ultraviolet exposure, and others can be utilized to determine their effect on the mechanical and electrical reliability of the devices.

As semiconductor packaging technologies continues to scale, it drives the use of existing and new materials in thin layer form factors. Additionally, packaging technologies continue to increase in complexity such as multi-chip packages, 3D packaging, embedded dies/passives, and system in package. This increasing packaging complexity implies that materials in thin layers are subject to non-trivial loading conditions, which may exceed the toughness of the material, leading to cracks. Furthermore, the continued focus on cost leads to a growing interest in novel, low-cost materials. It is important to ensure that the reliability of these low-cost materials is at par or better than currently used materials. This in turn, leads to significant efforts in the area of material characterization at the lab level to speed up the development process. The chosen test methods must not only provide accurate and consistent data, but they must also be applicable across a suitably wide range of materials to aid in the optimization process. Methods for testing and characterizing fracture induced failures in various material systems in electronic packaging are investigated in this paper. The learnings from the different tests methods are compared and discussed here. More specifically, different fracture characterization techniques on (a) freestanding ‘thin’ solder resist films, and (b) filled ‘bulk’ epoxy materials like underfills and epoxy mold compounds are investigated. For thin films, learnings from different test methods for measuring fracture toughness, namely, uniaxial tension (with and without an edge pre-crack) and membrane penetration tests, are discussed. The test methods are compared by characterizing several different thin films, to gauge how well each method could distinguish differences in material (and thickness). Reasonably good agreement was found between the various thin film toughness test methods; however, ease of sample preparation, fixture, and adaptability to environmental testing will be discussed. In the case of filled epoxy resin systems, the single-edge-notch bending (SENB) technique is utilized to obtain the fracture toughness of underfills and mold compounds with filler materials. Learnings on different methods of creating pre-cracks in SENB samples are also investigated and presented. Two methods are explored in this study, namely, razor blade and laser milling. Good agreement in fracture toughness values was obtained with the two precracking methods, along with considerations about ease of sample preparation and consistency of pre-crack dimensions also examined. Morphology of the pre-cracks obtained by these methods, and their effects on fracture toughness measurements, are also discussed.

The failure behavior of adhesive joints under shock-wave loadings was investigated in a large scale shock tube facility for the first time. An overlapping specimen consisting of two parts, one circular patch and one supporting ring were bonded together in a specially designed jig. Sub-miniature semi-conductor strain gauges were attached on the specimen to monitor the transient strain on specific locations. A high speed camera was used to record the detachment of the patch from the ring. Image processing tool was used to track the position of the patch as a function of time. This information yield estimates of velocity, acceleration and kinetic energy of the patch. A finite element model was also created and the computation results were compared to the experimental values obtained.

The increasing price of gold has resulted in industry interest in use of copper as alternative wire bonds interconnect material. Copper wire has the advantages of the lower cost, lower thermal resistivity, lower electrical resistivity, higher mechanical strength and higher deformation stability over the gold wire. In spite of the upside above, the Cu-Al wire bond is susceptible to the electrolytic corrosion and the reliability of Cu-Al wire bond is of great concern. Typical electronic molding compounds are hydrophilic and absorb moisture when exposed to humid environmental conditions. EMC contain ionic contaminants including chloride ions as a result of the chemical synthesis of the subcomponents of the resin, etching of metallization and the decomposition of the die-attach glue. The presence of moisture in the operating environment of semiconductor package makes the ion more mobile in the EMC. The migration of chloride ions to the Cu-Al interface may induce electrolytic corrosion inside the package causing degradation of the bond interface resulting in eventual failure. The rate at which the corrosion happens in the microelectronic packages is dependent upon the rate at which the ions transport through the EMC in addition to the reaction rate at the interface. In this effort, a multiphysics model for galvanic corrosion in the presence of chloride has been presented. The contaminant diffusion along with the corrosion kinetics has been modeled. In addition, contaminated samples with known concentration of KCl contaminant have been subjected to the temperature humidity conditions of 130°C/100RH. The resistance of the Cu-Al interconnects in the PARR test have been monitored periodically using resistance spectroscopy. The diffusion coefficients of chloride ion has been measured in the electronic molding compound at various temperatures using two methods including diffusion cell and inductively coupled plasma (ICPMS). Moisture ingress into the EMC has been quantified through measurements of the weight gain in the EMC as a function of time. Tafel parameters including the open circuit potential and the slope of the polarization curve has been measured for both copper, aluminum under different concentrations of the ionic species and pH values in the EMC. The measurements have been incorporated into the COMSOL model to predict the corrosion current at the Cu-Al bond pad. The model predictions have been correlated with experimental data.

Vortex generators have been widely used to enhance heat transfer in various heat exchangers. Out of the two types of vortex generators: Transverse vortex generators (TVGs) and longitudinal vortex generators (LVGs), LVGs have been found to show better heat transfer performance. Past studies have shown that the implementation of these LVGs can be used to improve heat transfer in thermoelectric generator systems. Here a built in module in COMSOL Multiphysics ® was used to study the influence of the location of LVGs in the channel on the comprehensive performance of an integrated thermoelectric device (ITED). The physical model under consideration consists of a copper interconnector sandwiched between p-type and n-type semiconductors and a flow channel for hot fluid in the center of the interconnector. Four pairs of, LVGs are mounted symmetrically on the top and bottom surfaces of the flow channel. Thus, using numerical methods, the thermo-electric-hydraulic performance of the ITED with a single module is examined. By fixing the material size D, the fluid inlet temperature T in , and attack angle β; the effects of the location of LVGs and Reynolds number were investigated on the heat transfer performance, power output, pressure drop and thermal conversion efficiency. The location of LVGs did not have significant effect on the performance of TEGs in the given model. However, the performance parameters show a considerable change with Reynold’s number and best performance is obtained at Reynold number of Re = 500.

Graphene is a promising material to design faster microprocessors given its exceptionally high thermal conductivity. However, due to its null electronic band gap, graphene must be combined with high-electric conductivity materials such as boron nitride to manufacture competitive alternatives to traditional semiconductors. Thus, the goal of this study is to determine the thermal conductivities and heat capacities of two-dimensional superlattices of graphene and boron nitride as a function of the secondary periodicity and interface orientation. We apply the Green-Kubo method to atomic trajectories calculated with Molecular Dynamics to determine the thermal conductivities of superlattices with periodicities between one and five in the armchair and zigzag orientations at 300 K. Results show that conductivities increase with decreasing periodicity, in good agreement with predictions made with Harmonic Lattice Dynamics. Thermal conductivities parallel to the interface are significantly higher than those perpendicular to the interface in the armchair configuration and vice versa in the zigzag orientation. Moreover, the heat capacities are practically independent of the periodicity and interface orientation up to 1500 K.

Two-dimensional superlattices are promising alternatives to traditional semiconductors for manufacturing power-dissipating devices with enhanced thermal and electronic properties. The goal of this work is to investigate the influence of the superlattice secondary periodicity and atomic interface orientation on the phonon properties and thermal conductivity of two-dimensional superlattices of graphene and boron nitride. We have employed harmonic lattice dynamics to predict the phonon group velocities and specific heats, and molecular dynamics to extract the relaxation times from normal mode analysis in the frequency domain. Density functional perturbation theory is applied to validate the phonon dispersion curves. The Boltzmann transport equation under single relaxation time approximation is then used to predict the thermal conductivities of the superlattices in the zigzag and armchair orientations with periodicities between one and five. Our results showed that the thermal conductivities increased by 15.68% when reducing the superlattice period from two to one. In addition, thermal conductivities parallel to the interface increase by 20.15% when switching the orientation from armchair to zigzag.

A tuning method was proposed for automatic lighting (auto-lighting) algorithms derived from the steepest descent and conjugate gradient methods. The auto-lighting algorithms maximize the image quality of the industrial machine vision by adjusting multiple-color light emitting diodes (LEDs), usually called color mixers. Searching for the driving condition for achieving maximum sharpness, which influences image quality, using multiple color LEDs, is time-consuming. Hence, the steepest descent and conjugate gradient methods were applied to reduce the searching time for achieving maximum image quality. The relationship between lighting and image quality is multi-dimensional, non-linear, and difficult to describe using mathematical equations. Hence the Taguchi method is actually the only method that can determine the parameters of auto-lighting algorithms. The Taguchi method was applied to an inspection system consisting of an industrial camera, coaxial lens, color mixer, image acquisition device, analog interface board, and semiconductor patterns for target objects. The algorithm parameters were determined using orthogonal arrays and the candidate parameters were selected by increasing the sharpness and decreasing the iterations of the algorithm, which were dependent on the searching time. After conducting retests using the selected parameters, the image quality was almost the same as that in the best-case parameters with a smaller number of iterations. The Taguchi method will be useful in reducing time-consuming tasks and the time required to set up the inspection process in manufacturing.

Thermoelectric generators (TEGs) are solid-state heat engines consisting of p-type and n-type semiconductors that convert heat into electricity via the Seebeck effect. Conducting polymers are a viable alternative with intrinsic advantages over their inorganic counterparts since they are abundant, flexible as thick-films, and have reduced manufacturing costs since they can be solution processed. Furthermore, polymers have an inherently low thermal conductivity, thus affording them the option of forgoing some heat exchanger costs. Current examples of polymer TE devices have been limited to traditional flat-plate geometries with power densities on the μW/cm 2 scale, where their potential is not fully realized. Herein, we report a novel radial device and evaluate the improved performance of polymer-based TEG based on this architecture. Analytical heat transfer and electrical models are presented that optimize the device for maximum power density, and we obtain the geometry matching condition for this radial device that maximizes the module figure-of-merit. Our radial architecture accommodates a fluid as the heat source and can utilize natural convection alone (due to heat spreading) to obtain high power densities of 1–3 mW/cm 2 using state-of-the-art polymer TEs subjected to a temperature difference of 100 K.

Gold wire bonding has been widely used as first-level interconnect in semiconductor packaging. The increase in the gold price has motivated the industry search for alternative to the gold wire used in wire bonding and the transition to copper wire bonding technology. Potential advantages of transition to Cu-Al wire bond system includes low cost of copper wire, lower thermal resistivity, lower electrical resistivity, higher deformation strength, damage during ultrasonic squeeze, and stability compared to gold wire. However, the transition to the copper wire brings along some trade-offs including poor corrosion resistance, narrow process window, higher hardness, and potential for cratering. Formation of excessive Cu-Al intermetallics may increase electrical resistance and reduce the mechanical bonding strength. Current state-of-art for studying the Cu-Al system focuses on accumulation of statistically significant number of failures under accelerated testing. In this paper, a new approach has been developed to identify the occurrence of impending apparently-random defect fall-outs and pre-mature failures observed in the Cu-Al wirebond system. The use of intermetallic thickness, composition and corrosion as a leading indicator of failure for assessment of remaining useful life for Cu-al wirebond interconnects has been studied under exposure to high temperature and temperature-humidity. Damage in wire bonds has been studied using x-ray Micro-CT. Microstructure evolution was studied under isothermal aging conditions of 150°C, 175°C, and 200°C till failure. Activation energy was calculated using growth rate of intermetallic at different temperatures. Effect of temperature and humidity on Cu-Al wirebond system was studied using Parr Bomb technique at different elevated temperature and humidity conditions (110°C/ 100%RH, 120°C/ 100%RH, 130°C/ 100%RH) and failure mechanism was developed. The present methodology uses evolution of the IMC thickness, composition in conjunction with the Levenberg-Marquardt algorithm to identify accrued damage in wire bond subjected to thermal aging. The proposed method can be used for quick assessment of Cu-Al parts to ensure manufactured part consistency through sampling.

The interface mixing of metal-organic semiconductor layers plays a remarkable role in thermal transport in organic electronic devices. Here we apply the lattice Boltzmann method (LBM) to simulate the effect of the interface mixing on thermal boundary conductance (TBC) of Ag-pentacene and Ag-CuPc thin films. The spring constant-dependent transmission coefficient is considered in the simulation to investigate the effect of the interfacial bonding on TBC. The simulation result is compared with the experimental result of Ag-CuPc thin film obtained by other research group. By varying the thickness and composition of the intermixing layer, a significant variation of the thermal boundary conductance of the thin film is observed. The total thermal boundary conductance will increase with the spring constant per area. The increase of the thickness of the intermixing layer leads to the downward trend of the total thermal boundary conductance and it is attributed to the enhancement of the intrinsic thermal resistance of the intermixing layer. These findings suggest the interfacial bonding, thickness and composition of the metal-organic intermixing layer should be carefully controlled to achieve the desired thermal boundary conductance.

Manufacturing process for complex and heterogeneous systems in sub-millimeter scale requires several discontinuous and expensive steps. Batch manufacturing approach via legacy semiconductor processes often do not provide a viable solution for such type of product development due to either their inherent limitations of monolithic and in-plane design or commercial unsuitability in cases of low to medium production volumes. Therefore, alternative approaches, such as microassembly techniques, are warranted for this type of advanced manufacturing requirements. However, lack of standards for design and unavailability of off-the-shelf robotic assembly systems, augmented with scaling of physics in micro-domain, eventually renders the highly iterative approach toward product development cycle cost-inefficient and time-consuming. In ordered to deal with this compounded problem in micromanufacturing, it becomes imperative that a holistic approach be employed that develops not only the product but also the system that is used to construct the same. In our work, we demonstrate this concurrent engineering approach through a novel, analytical framework, called as “Design for Multiscale Manufacturability (DfM 2 )”. This framework, built into an interactive software application, enables the user to estimate common manufacturability metrics such as process yield, cycle time, overall cost and device performance, which improves the decision making in production and paves the pathway to commercialization by reducing the time and cost to market. Furthermore, we also demonstrate the implementation of the DfM 2 application in evaluating the manufacturing of heterogeneous microsystems by a custom developed modular and reconfigurable manufacturing cell (MRMC). A real case-study has been discussed for the implementation of the DfM 2 .

Advances in semiconductor technology and trends in slim and light electronic systems have led to a significant increase in heat dissipation density of the electronic devices. Therefore, effective cooling technology is essential for reliable operation of electronic components. Among various cooling systems, natural convection heat sinks have been proven to be appropriate because of their inherent simplicity, reliability, and low long-term cost. The present study is focused on natural convective heat transfer from the cylindrical heat sink. Especially, the branched fins, which are motivated by the branched design of nature shown in trees and lungs, are used. The heating power and surface temperature are measured for various types of branched fins and numbers of fins. The result showed that the branched fin dissipates 20% more heat compared to the normal plate fins. Therefore, heat sinks with branched fins have a potential as a next-generation cooling device.

The metal organic chemical vapor deposition (MOCVD) process is widely used to form a multi-layered structure with thin films for diverse semiconductor materials. The MOCVD process is the most promising method for manufacturing chips that are based on the compound semiconductor, but its technology is partly still insufficient. If a device, for example, lacks a non-uniformity related to the composition and thickness of the film, it decreases the reliability of the final product and affects the economics. To ensure that the equipment is competitive in the worldwide markets, a high reliability including the controllability of compositions is required for the equipment. In this study the CFD analysis was used to investigate the behavior of the process gas in a MOCVD reactor where the process gases including the component of the GaN films are injected as separated through a multi-module showerhead for eventually targeting multi-component films such as AlGaInN materials. After applying of Porous Media, a stabilization of process gas was confirmed from the results of pressure distribution.

Three dimensional (3D) stacking of semiconductor chips is an emerging technology which promises improved electrical performance including improved bandwidth, reduced wire interconnection lengths, and reduced signal delay. However, due to the higher power density per unit volume of the stacking, it poses great challenge for thermal management. Inter-tier microfluidic cooling with microgaps with surface area enhancements such as pin fins can potentially achieve superior thermal performance. As such, the hydraulic and thermal characteristics of this configuration over parametric ranges of practical interest are important. Conventional correlations developed in the literature for macropin fins show large errors for dense arrays of micropins. In this work, the hydraulic and thermal characteristics of a microgap with pin fin were investigated for a large range of Reynolds number (Re) based on pin fin diameter (D p ) by numerical modeling. The effects of the pin fin dimensions including diameter, transversal spacing, longitudinal spacing, height and Re on the friction factor (f) and colburn j factor were studied. Correlations of the f and j for dense arrays of micro pins are developed based on parametric runs over 22< Re <357, pin fin diameter of 100 μm, pitch/ diameter ratios of 1.5 ∼ 2.25, and height/ diameter ratios of 1.5 ∼ 2.25. The validity of the correlations is confirmed by experiments. Lastly, a parametric optimization was done and the thermal resistance of the microgap with 150 W heat generation is reduced by 28.5% with the optimized dimensions for a given pumping power compared to an un-optimized pin fin configuration.

A reduced-order model of a Microfluidic Transistor is presented. The transistor is essentially a long micro channel between substrate and a membrane that is pressure actuated. The proposed model captures steady (DC) and small signal (AC) behavior of the device in a manner analogous to standard semiconductor transistor models. The model is based on steady and perturbed unsteady solutions of the conservation of mass and momentum, coupled with an elastic model for the membrane. To improve the accuracy and to enhance the range of validity, the model is enhanced by numerical simulations of the coupled fluid-structure problem. The model predicts dependence of the transconductance on the pressure differentials across the membrane and along the channel. The proposed model also investigates the impact of flow inertia, among other effects, on the dynamic behavior of the transistor.

The low temperature furnace for semiconductor processing is applicable not only to the equipment which needs heat treatment on the silicon wafer but also to the industry field similar to semiconductor manufacturing. The target process in this research is for the low temperature furnace less than 500°C. The investigation on controlling the flat zone at low temperature range has been important with the recent development trend of miniaturized device and new materials. When the temperature in the furnace is changing, the temperature changing rate is slower at the batch type than the single type. The thermal problems therefore occur including the unnecessary heat treatment and the thermal shock of wafer for the sudden heat change. The research target is therefore to obtain the uniform temperature distribution in a whole furnace when manufacturing the low temperature heat treatment equipment. The precise control of the temperature of the reactor is a crucial factor obtaining the vapor deposition uniformity on the wafer surface. In this research, we validate the reliability of numerical analysis by being compared with the experimental results. And the different parameters that affect the internal temperature distribution including the radiant heat transfer are investigated using CFD for designing and manufacturing the furnace. To obtain the uniform temperature distribution of the reactor, the emissivity and reflectivity of pedestals which are installed under the wafer cartridge are also changed and investigated along with the different number of pedestals and distance of pedestals from the bottom of the wafer cartridge. As the results, the most effective design factor is the temperature of each heater to make the wafer temperature uniform. Additionally, the yield rate per one process is increased when the number of wafers is increased because the flat zone is widened.