The drive towards increased functional integration and improved performance in microelectronic devices has led to the introduction of more layers and porous dielectric materials in back end of line (BEOL) stack. These materials have low mechanical strength as well as adhesive strength and thus, interfacial delamination is a major reliability concern for modern microelectronic devices. In this work, we present a cohesive zone element based finite-element model to predict failures observed at the end of flip-chip assembly reflow process. During lead-free flip-chip assembly, thermo-mechanical stresses arise due to the coefficient of thermal expansion (CTE) mismatch between the organic substrate and the silicon die. Such stresses can be high enough to cause cracking of interlayer dielectric layers present in the vicinity of solder bump. In order to predict such failures, mixed mode cohesive zone parameters are first extracted from interfacial fracture characterization experiments of real-life BEOL stacks. Then, the characterized cohesive zone elements are embedded in 2D finite-element models of flip-chip assembly to predict the failure region. The predicted failure region is compared against 2D fracture mechanics based models as well as failure analysis experiment results. Cohesive zone elements are then implemented over multiple bumps to examine simultaneous failure of multiple bumps under reflow assembly, and thus, the effectiveness of cohesive zone elements compared to fracture mechanics approach is demonstrated.

Large-scale integration at lower cost has led to the usage of multi-layered organic substrates in flip-chip assemblies. However, the warpage of substrate plays an important role in the reliability of back-end-of-line (BEOL) stack on a chip. In this work, we study the effect of substrate layer configuration, and thus the warpage of the substrate at reflow temperature on BEOL reliability. A plane-strain flip-chip on substrate assembly model is utilized to study the die and solder stresses for different substrate layer configurations. Apart from studying the die stresses, fracture mechanics based approach is used to study the effect of substrate configuration on energy available for a crack present in back-end-of-line (BEOL) stack. In this paper, we describe the methodology to model the substrate with initial warpage at reflow temperature, characterize the effect of the initial warpage at reflow temperature on die stresses at room temperature and further use fracture mechanics based approach to predict the change in risk for a crack present in BEOL stack for different substrate warpage configurations at reflow temperature.

In the conversion to Pb-free electronics, there has been increasing interest in conductive adhesive interconnects, as they combine Pb-free materials with the added benefit of low temperature processing. This work explores the degradation mechanisms and kinetics in adhesively bonded Au-bumped flip chip interconnects. Earlier researchers have suggested that electrical contact is by mechanical interfacial compression caused cure-induced shrinkage of the adhesive and degradation is by stress relaxation of the adhesive material during temperature and moisture cycling throughout the life cycle. However, temperature cycling conducted here raises questions about the validity of this hypothesis since no such progressive degradation is found under temperature cycling. Instead, overstress failures were found at cold temperatures. The alternate interconnection mechanism between the Au bumps, suggested by this study, is metallurgical bonding by cold welding or mechanical interlocking. Experimental and modeling results showing evidence of this cold welding phenomenon are presented here. First, the surface roughness of unmated and mated Au bumps are characterized on flip-chip dies, since the amount of surface flattening provides insights into both mechanical interlocking as well as propensity for cold-welding. A corresponding elastic-plastic, large-deformation finite element modeling with nonlinear contact surfaces is used to further understand and quantify this surface-flattening phenomenon. Next, pull tests for flip-chip to flip-chip assemblies were designed to measure the bond strength and observe the temperature & time dependence of the strength at the interface. The results clearly showed strong evidence that the bonding mechanism may be either diffusionassisted metallurgical bonding or increase in contact area over time due to new bond formation. This work is somewhat novel, as prior examples of low-temperature cold welding are mostly for very thin gold films.

In the present study, 2 different composite solder systems were successfully synthesized using powder metallurgy route consisting of: blending, compaction, sintering and extrusion. The Sn-Ag-Cu based composite solders were reinforced with namely, titanium diboride (TiB 2 ) particulates and multi-walled carbon nanotubes (MWCNTs). The extruded materials were then characterized for their electrical resistivity values using the four-point probe setup from Jandel. The electrical resistivity results showed no degradation of electrical performance of the composite solders, except at high volume percentages of TiB 2 addition. This signified that with judicious selection of the reinforcement type and the amount of reinforcement addition, these advanced interconnect materials will benefit industries like the microelectronics flip chip assembly and packaging, MEMS systems and NEMS systems.

It is well established that Pb free alloys tend to solder less readily than Sn/Pb. It is not clear that this is always a major problem, but two factors combine to make it more of a concern for flip chip than for other applications. Not surprisingly, wetting and spreading appears to become less effective as the solder volume is reduced and a larger fraction of it is near the surface. At the same time assembly yields tend to become more sensitive to this. The present paper addresses the assembly of flip chips with Sn/Ag/Cu bumps onto Ni/Au and OSP coated copper pads on organic substrates. Soldering defects observed included incomplete wetting and collapse, as well as poor self centering. The sensitivity to fluxes, reflow profiles, and substrate pads were investigated and potential consequences for assembly yields calculated numerically.

Electrically conductive adhesives are emerging as a lead free, flux less, low temperature alternative to soldering in a variety of electronics and optoelectronics applications. Some of the potential benefits are obvious, but so far the adhesives have some limitations as well. The present work offers a critical evaluation of one approach to flip chip assembly, which lends itself particularly well to use with a high speed placement machine. Wafers were bumped by stencil printing of a thermoset conductive adhesive, which was then fully cured. In assembly, the conductive adhesive paste was stencil printed onto the pads of a printed circuit board and cured after die placement. The printing process was optimized to ensure robust assembly and the resulting reliability assessed.

Usually, flipchip technology is based on either high-Pb or eutectic Sn/Pb solder forming the connections between the semiconductor chip and the carrier substrate. However decay of the 210 Pb constituent, via 210 Bi and 210 Po, to 206 Pb involves the emission of energetic alpha particles which have a tendency to cause soft errors in nearby active elements on the chip. Also, impending legislations in Europe and Japan on the elimination of Pb from electronic products have prompted the investigation of alternative solder alloys. This paper outlines an initial development effort focussed on the Sn/Ag/Cu (95.8/3.5/0.7) alloy. The study involved the development of a flip chip assembly process followed by a reliability evaluation comparing the fatigue resistance of the Sn/Ag/Cu alloy to that of eutectic Sn/Pb solder. The test vehicle used was a 225μm bump pitch, 11mm square die mounted on a ceramic substrate.

In development of surface mount technology for Ball Grid Array (BGA) or flip-chip assemblies, it is important to reduce stress concentration in solder joints as it is immediately effective in improving the fatigue life of the assembly. Thus, the ability to predict and control the joint geometries is critical to obtaining robust and reliable designs of interconnects. Other than the issue of the bump shape, there are many problems concerning soldering such as bridging or self-alignment in which surface tension is definitely involved. This paper attempts to apply the FEM approach in solving these problems. Rigid-plastic FEM which is based on iteration for the velocity field in an incompressible viscous fluid is an approach to large deformation analysis. The flow stress is described by the viscosity of the fluid and the strain rate. By introducing an automatic mesh updating procedure, transient problems with free boundary can be treated. We applied this concept to the prediction of solder joint shapes. In this kind of problem, effects of surface tension dominate. Since surface tension is a distributed load that depends on surface curvature, we employed 2D and 3D methods in which the load is updated based on instantaneous state of surface. To verify the accuracy of this method, we analyzed some shape and stability problems of liquid drops for which theoretical solutions were given. Practical applications of the method were also performed for the 2D and 3D solder joint problems, and the results showed a good agreement with experimental ones.

In this paper, the development of wafer level packaging of radio frequency (RF) microelectromechanical system (MEMS) is reported. The packaging process consists of wafer bonding, wafer thinning, via etching, plating, under-bump-metallization (UBM) and bumping processes. 6-inch Si and glass wafers are used in the study. RF MEMS devices are fabricated on Si wafers and sandwiched between Si and glass cap wafers. To maintain the pressure balance between the cavities and outside world after bonding process, Si and glass wafers are anodically bonded at a pressure of 2 bar and a bonding temperature of 400 °C. The cavities are hermetically sealed. The glass wafer of the bonded pair is thinned down to 100 μm using mechanical polishing and chemical etching, the good uniformity of the wafer thickness is maintained with etching process. A layer of Cr/Au is sputtered and patterned as the hard mask for glass via etching process. Via holes with undercut closer to the etching depth are formed in HF+HNO 3 acid. After stripping the metal mask, a seed layer of TiW/Cu is deposited using sputtering and plating processes. TiW layer is used to enhance the adhesion of metal and glass. With the completion of the re-routing and via metallization processes, benzocyclobutene (BCB) photoresist is used to planarize via holes and opened for UBM process. Finally, the packaged devices can be assembled using flip chip approach.

This study addresses the development of lead-free nanocomposite solders. Lead-free composite solders were successfully synthesized, with varying amount of nanosized Y 2 O 3 particulates incorporated into 95.8 Sn - 3.5 Ag - 0.7 Cu solder. These composite materials were fabricated using the powder metallurgy technique involving blending, compaction, sintering and extrusion. The extruded materials were then characterized in terms of their physical properties, microstructural development, thermal and mechanical properties. Results revealed that with the incorporation of increasing amount of reinforcements, the density values of the composite solders decreased while their corresponding porosity levels increased. Thermomechanical analysis of the solder nanocomposites showed that the use of reinforcements lowered the average coefficient of thermal expansion of the solder materials. Moreover, the results of mechanical property characterizations revealed that the addition of reinforcements aids in improving the overall strength of the nanocomposite solder. Particular emphasis is placed in this study to correlate the effect of increasing presence of Y 2 O 3 particulates with the properties of the resultant nanocomposite materials. These advanced interconnect materials will benefit industries like the microelectronics flip chip assembly and packaging, MEMS systems and NEMS systems.

In this work, we report on our efforts to develop high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. −55 to 150 °C). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR ® ). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics. Other experimental testing has demonstrated that the new laminate successfully passes toxicity, flammability, and vacuum stability testing as required for pressurized and un-pressurized space applications.

In this study, Sn-Ag-Cu based nanocomposites with carbon nanotubes (CNTs) as reinforcements were successfully synthesized using the powder metallurgy technique. Micron size lead-free solder particles were blended together with varying weight percentages of CNTs. Blended powder mixtures were then compacted, sintered and finally extruded at room temperature. The extruded materials were characterized for their melting temperatures, wettability and mechanical properties. Experimental results revealed that the melting temperatures of the composite solders did not have any significant changes. Wettability property of the composite solder was also found to improve with addition of reinforcements. Moreover, the results of mechanical properties characterization exhibited an increase in overall strength of the composite solders. An attempt is made in the present study to correlate the variation in weight percentages of reinforcement with the properties of the resultant nanocomposite materials. These advanced interconnect materials will benefit industries like the microelectronics flip chip assembly and packaging, MEMS systems and NEMS systems.

Flip chip packaging is one of the fastest growing segments in electronics packaging technology. The semiconductor packaging industry is continuing to migrate towards Pb-free electronics assembly. Therefore, the development of compatible materials for Pb-free flip chip packaging is critical to this transition [1]. Flip chip devices are commonly underfilled to compensate for the mismatch in the Coefficient of Thermal Expansion (CTE) between the die and the chip carrier. The No Flow Underfill (NFU) process is a type that can increase the throughput of the flip chip assembly process and reduce manufacturing costs. Significant research has been performed to develop NFUs for eutectic applications. However, further research is required for the development of NFUs that are compatible with the Pb-free solders and the high temperature reflow process associated with these solders. In this paper, the challenges associated with the development of 'filled' underfill formulations for assembly with the 95.5Sn/3.8Ag/0.7Cu bumped flip chip devices are discussed. The effects of process variables that affect voiding in the underfill layer have been presented. The impact on voiding due to stencil printing of the underfill has been discussed. The impact on assembly reliability due to the underfill material properties has also been reported.