As Integrated Circuit (IC) device sizes shrink, intrinsic and thermo-mechanical stress in interconnects is an ever increasing reliability concern. Increasing device density leads to more interconnect layers and hence, greater probability of stress related failure through mechanisms such as electromigration, delamination and voids. Current state-of-the-art IC technology uses 5 interconnect layers. According to the 1997 SIA Roadmap, that number is expected to increase to 9 by the year 2012 [1]. As a result, methods to measure, model and reduce stresses in interconnects are needed to manufacture reliable, future generation IC’s.

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