In this paper, a non-linear finite element framework was established for processing mechanics modeling of electronic packaging assemblies and layered manufacturing. In particular, topological change was considered in order to model the sequential steps during a typical IC package assembly. Geometric and material nonlinearity, temperature-dependent material properties were considered. Different stress-free temperatures for different elements in the same model were used to simulate practical manufacturing process-induced thermal residual stress field in the chip assembly. As comparison, two FEM models (Processing Model and Non-Processing Model) of a encapsulated IC package considered, associated with different processing schemes, were analyzed. From the finite element analysis, it is found that due to the coefficient of thermal expansion (CTE) mismatch between the solder and silicon chip, the substrate and the solder, there exist very high stress fields near these interfaces when the encapsulated IC package is cooled down to room temperature after processing for these two models. But in contrast with the stresses near the edges of all interfaces obtained from Non-Processing Model, the stresses near the edges of all interfaces corresponding to Processing Model are generally higher than those obtained from Non-Processing Model. In particular, the Von Mises stress at the edge of silicon chip/solder interface obtained from Processing Model is nearly 50% higher than that obtained from Non-Processing Model. It is shown that Processing Model which is based on the FEM framework established in this paper can more realistically simulate a series of practical manufacturing processes in the chip assembly, whereas a larger error can be caused by using Non-Processing Model in the analysis of process-induced residual stress field in the packaging assemblies due to the negligence of the bonding process during cooling from 250° C to 160° C.

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