The objectives of this research were to address some reliability issues in flip chip applications by characterizing the stress and strain response of a flip chip assembly under various loading conditions. In particular, the issue of fundamental limits on chip size was addressed and the importance of appropriate material models and constitutive relationships was assessed. Linear thermoelasticity models, metal plasticity models, viscoelasticity models and creep models were implemented. Finally, parametric studies were performed to optimize some of the elastic properties of the underfill.
It has been shown that (1) the chip major dimension is not the limiting factor in determining the maximum chip size for underfilled flip chip interconnections; (2) non-linear material behavior (e.g., creep, viscoplasticity, etc.) and detailed geometry need to be considered in the modeling to accurately predict the stress and strain fields; (3) there is an window for selecting optimal thermal expansion coefficient and modulus values which minimize stress and strain fields in the solder and silicon chip.