The thermo-mechanical reliability of electronic packages such as flip chip assemblies and chip scale packages is one of the most important conditions for adopting these technologies in industrial applications. On the other hand, various kinds of inhomogeneities, localized stresses and thermal mismatch between the silicon die and the substrate lead to interface delaminations, chip cracking and fatigue of solder interconnects.
The contribution shows the use of nonlinear finite element simulations with respect to the nonlinear, temperature and rate dependent behavior of the different materials used (metals, polymeric and solder materials) and the combination with experimental investigations. The development and application of failure models (e.g. thermal fatigue, life time prediction by Coffin-Manson type equations, integral fracture mechanics approaches — J–, –, ΔT*– integral — and evaluation of critical regions) is explained, in detail.
Furthermore, the simulation of damage growth in solder interconnects by an automatic adaptive finite element technique is performed. Inherent local damage models allow us to study the correctness of crack- and damage models. For this reason, some results have been compared to micrographs from damaged interconnects and to strain measurement results obtained by experimental methods. In particular, the microDAC measurement method is a powerful tool which inspects the displacement fields on the basis of the gray scale correlation method applied to micrographs from scanning electron microscopy, laser scanning microscopy and optical microscopy.
The application of those combined investigations should help to better understand the failure mechanisms especially in solder joints and directly support further applications for enhancing the thermo-mechanical reliability of advanced electronic assemblies.