Self heating diminishes the reliability of SOI transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated in part by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, ds, to a value nearly 40 percent less than that of bulk silicon for ds = 0.42 μm. The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples, which results from the BESOI wafer fabrication process. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The data provided here will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

This content is only available via PDF.
You do not currently have access to this content.