Self Heating in III-V Transistors

The III-V integrated-circuits industry makes use of measured and modeled thermal impedances to model and to optimize transistor performance and to design circuits. In field effect transistors (FETs), heat is generated in a very small volume on the drain side of the gate, but models assume that it is generated in wide rectangular bars on the surface of the device. We describe electrical techniques for measuring the thermal impedances in FETs and in heterojunction bipolar transistors (HBTs). In HBTs the maximum power densities are limited by self heating, and we describe experimental studies of thermal shunt designs that reduce the thermal impedances.