Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced 3D IC technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in MOSFET/FinFET electrical characteristics is highlighted. A physics-based compact modeling methodology for multi-scale simulation of all contributing components of stress induced variability is described. A simulation flow that provides an interface between layout formats (GDS II, OASIS), and FEA-based package-scale tools, is also developed. This tool, can be used to optimize the floorplan for different circuits and packaging technologies, and/or for the final design signoff, for all stress induced phenomena. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with correlation of the electrical characteristics to direct physical strain measurements.

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