Three-dimensional (3D) stacking is an emerging trend for future high performance microsystems. The stacking of chips increases the power density significantly, with associated thermal concerns. For interior tiers in a 3D stack, the surface area for the heat removal is further reduced. Also, realistic power maps on active tiers produce highly non-uniform patterns, with maximum heat fluxes 5–10 times the average values. Conventional air-cooled heat sinks cannot meet these thermal requirements. In this paper, a compact thermal model of a multi-layer chip stack subjected to the realistic power map was developed. Interlayer pin fins were modeled on the back of the chips, with water as the coolant. It was found that the compact model ran ten times faster than the full computational fluid dynamics/heat transfer (CFD/HT) model, with errors within 5%. The compact model was then used to analyze the thermal characteristics of 4 layer stacked dual core Penryn microprocessors, with a total power of 172.4 W. The non-uniform power map produced maximum heat flux of 300 W/cm2 in the hot spots. The results show that at a pressure drop of 20 kPa and inlet water temperature of 20 °C, the temperature of the bottom tier is higher than the other three tiers and the maximum temperature of the bottom layer is 56 °C. This is because the bottom layer thermal management only depends on one-sided pin fin cooling, while the other layers have double-sided cooling. A dual pass channel configuration reduced the maximum temperature to 50 °C. Overall, the interlayer pin fin cooling was found to be a very effective thermal management method for 3D stacked die packaging.

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