Analysis of TSV/Micro-Bump Deformation due to Chip Misalignment and Thermal Processing in 3D IC Packages

Misalignment of chips in three-dimensional (3D) integrated circuit (IC) packages subjects the bonding layer between chips to shear deformation. Chip warpage and thermal effects from chip processing can further compound the problem. In this study we perform a numerical assessment on the shear and thermally-induced deformations in and around the through-silicon vias (TSV) and solder micro-bumps. The 3D finite element model features a TSV/micro-bump bonding structure connecting two adjacent silicon chips, with and without an underfill layer in between. The possibility that the entire solder micro-bump may be transformed into an intermetallic is also considered in this study. We seek to parametrically explore the trend of stress and deformation fields due to misalignment-induced shear deformation and thermal expansion mismatch. Potential for damage initiation in the TSV/micro-bump is examined by the measure of plastic strain accumulation. The existence of an underfill layer around the TSV/micro-bump enhances the overall resistance to shear deformation, although with a higher buildup of local stresses. The TSV and silicon chip are less affected by misalignment than by thermal expansion mismatches.