Miniaturization and more recently convergence have been driving the industry since the invention of the transistor and integrated circuit (IC). While gate delay has decreased with transistor scaling, the increase in the resistive capacitive (RC) delay due to shrinking interconnect dimensions has become a serious concern for the development of future-generation electronics. To reduce the delay due to resistance R, a major technology change was the replacement of Aluminum (Al) with Copper (Cu) interconnects. Recently, some investigators have suggested using low-k dielectric (having dielectric constant less than 4) instead of Silicon dioxide (k = 3.9) to reduce the capacitive component in the RC delay. Recent research has shown low-k materials to have characteristics such as low mechanical strength and adhesion. In this paper, thermo-mechanical analysis of a single chip flip-chip module (SCM) consisting of a die integrated with low-k dielectric medium, substrate, solder balls, and a printed circuit board (PCB) is performed. The analysis is done in two steps within the ANSYS finite element software to account for thermally induced stresses due to mismatch in thermal expansion coefficient. In the first step, the thermal analysis is carried out to derive the steady state temperature distribution within the package under the imposed power rating. In the second step, the evaluated temperature field is utilized in a coupled thermo-mechanical structural analysis. The developed framework is utilized to study the thermo-mechanical behavior of various low-k dielectrics, wherein the stresses and strain distributions within the chip region are quantified. The analysis has shown no change in the temperature distribution between the base case of Silicon dioxide (SiO2) and low-k materials. The maximum equivalent stress in the package, for all the four dielectric cases (SiO2, polyimide, Hydrogen Silsesquioxane, and Black diamond) is seen in the silicon region of the die and that it does not change with the dielectric materials. However, the maximum equivalent stress in the low-k/metal layers varies with the materials but is always few orders of magnitude less than their corresponding yield strengths. Comparative analysis between Silicon dioxide (SiO2) and different low-k materials will help in identifying the weak spots in low-k dielectric when exposed to standard user environments.

This content is only available via PDF.
You do not currently have access to this content.