The convergence and miniaturization of the consumer electronic products such as cell phones and digital cameras has led to the vertical integration of packages i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful tool that satisfies such Integrated Circuit (IC) package requirements. 3-D technology looks to be the future of hand-held electronics; hence, making it an important research area. Stacked chips are peripherally interconnected through wires; this increases the package size and usually requires an extra “interposer” layer between the chips, causing substantial delays. Due to high package density and chip-stacking on top of each other, heat dissipation from the die becomes a concern. To overcome these thermal challenges and provide better inter-chip and chip-substrate electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D electronics. Electrical interconnection and heat dissipation improves with the number of TSVs. But, there is a trade-off; TSVs occupy the chip real estate, resulting in reduced silicon efficiency when compared to the baseline (no-TSV) scenario. Coefficient of thermal expansion (CTE) mismatch and reduced chip area causes thermal stresses and may lead to premature chip failures. This can be a major reliability issue. In this paper, a parametric study of the number of TSVs in a test vehicle (TV) consisting of 2 vertically stacked dies and TSVs (between the die and the substrate) has been performed using ANSYS WORKBENCH. A quarter symmetry model has been formulated to study the various cases as a function of number of TSVs. Each die has an area of 5.7mm2 with 0.1-mm thickness and 0.5W power rating. The TSV diameter is 50-μm each with a SiO2 insulation film of 25-μm thickness. Junction temperature and thermal resistance is determined to obtain the best case in terms of temperature distribution on the die. Furthermore, thermo-mechanical analysis is performed for all the TSV configurations and a guideline is proposed based on thermal and structural response.
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ASME 2010 International Mechanical Engineering Congress and Exposition
November 12–18, 2010
Vancouver, British Columbia, Canada
Conference Sponsors:
- ASME
ISBN:
978-0-7918-4447-2
PROCEEDINGS PAPER
Coupled Thermal and Structural Parametric Analysis of TSVs in 3D Electronics
Fahad Mirza,
Fahad Mirza
University of Texas at Arlington, Arlington, TX
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Bharathkrishnan Muralidharan,
Bharathkrishnan Muralidharan
University of Texas at Arlington, Arlington, TX
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Poornima Mynampati,
Poornima Mynampati
University of Texas at Arlington, Arlington, TX
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Dereje Agonafer
Dereje Agonafer
University of Texas at Arlington, Arlington, TX
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Fahad Mirza
University of Texas at Arlington, Arlington, TX
Bharathkrishnan Muralidharan
University of Texas at Arlington, Arlington, TX
Poornima Mynampati
University of Texas at Arlington, Arlington, TX
Saket Karajgikar
Future Facilities Ltd.
Dereje Agonafer
University of Texas at Arlington, Arlington, TX
Paper No:
IMECE2010-40803, pp. 675-680; 6 pages
Published Online:
April 30, 2012
Citation
Mirza, F, Muralidharan, B, Mynampati, P, Karajgikar, S, & Agonafer, D. "Coupled Thermal and Structural Parametric Analysis of TSVs in 3D Electronics." Proceedings of the ASME 2010 International Mechanical Engineering Congress and Exposition. Volume 10: Micro and Nano Systems. Vancouver, British Columbia, Canada. November 12–18, 2010. pp. 675-680. ASME. https://doi.org/10.1115/IMECE2010-40803
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