The coefficient of thermal expansion (CTE) mismatch between a die and an organic substrate generates high stresses in the die when underfilled solder bumps are used. These high stresses could crack or delaminate low-K dielectric materials in the next-generation flip-chip devices. In addition to such on-chip failures, the solder interconnects could fail due to thermo-mechanical fatigue, especially when the interconnect dimensions are scaled down to meet fine-pitch requirements. To address these reliability issues, compliant interconnects have been proposed to alleviate the thermo-mechanical stresses in the chip assembly. Some of the challenges to be addressed with compliant interconnects are: higher electrical parasitic compared to solder bumps, cost-effective fabrication, and high-yield, fine-pitch assembly process. This paper presents a study on a parallel-path compliant interconnect design which attempts to balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Also, these interconnects can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermo-mechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermo-mechanical reliability of a parallel-path compliant interconnect.

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