Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, memory controller, etc. has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional units dissipate little or no power. This highly non-uniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effects on computer performance, product reliability, and yield. Moving the functional units may reduce the junction temperature but can also affect performance by as much as 30%. In this paper, multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. From the results, the minimum and the maximum temperature was 56.6°C and 62.2°C with a corresponding penalty on the performance of 14% and 0% respectively. The numerical analysis was performed for 90 nm Pentium® IV Northwood architecture at 3 GHz clock speed.

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